臺灣博碩士論文加值系統

本論文研究方向為設計一個可執行Java Card Bytecode的Java Card Microcontroller。它的架構是一個16位元的Stack Machine 處理器。除了對Java Card 2.1.1 Bytecode 指令集的分析與分類外，設計時主要著重記憶體使用率的分析及改善堆疊機器的執行效能。此處理器使用硬體描述語言來實現Bytecode指令集，並使用Java Card Applet的程式驗證Java Card Microcontroller的正確性，並將整個電路載入到FPGA的晶片上和單晶片及PC連接進行整個系統電路的測試與驗證。目前版本除部份物件導向之特殊指令及選項之32位元指令外，均已完成。使用碼錶量測應用程式之效能和GemXpresso 211 PK Java Card比較，有10~18之效能提昇(speedup)。

This paper is to design and implement a Java Card Microcontroller. The microcontroller is 16-bit stack machine that implements the Java Card 2.1.1 instruction specifications. Focus is made on analyzing the memory utlization to further improve its performance. It is first implemented by Verilog HDL, followed by a simulation together with a Java Card Application, a wallet applet (e-purse). Finally, the implementation is downloaded into a FPGA chip and operations effectively on an evaluation target board. Current version does not support some object related instructions, and those 32-bit optional instructions. A performance benchmark shows that there is a 10~18 speedup as compared with GemXpresso 211 PK Java Card.

中 文 摘 要....................................i
Abstract.......................................ii
致謝...........................................iii
章 節 目 錄....................................iv
表目錄.........................................vi
圖目錄.........................................vii
第一章 緒論....................................1
1-1 研究相關背景...............................1
1-2 研究動機與目標.............................2
1-3 章節概要...................................3
第二章 Java Card介紹...........................4
2-1 Java Card與Smart Card......................4
2-2 Java Card Bytecode指令集...................6
2-3 Java Card軟硬體相關之介紹..................8
2-3-1 Java Card硬體介紹........................8
2-3-2 Java Card軟體介紹........................11
2-4 ISO7816相關規格............................12
2-5 Java Card系統架構..........................13
第三章 Java Card Microcontroller設計...........14
3-1 系統設計流程...............................16
3-2 指令集分析.................................17
3-2-1指令集分類................................17
3-3 Java Card Microcontroller效能評估..........20
3-3-1 Bytecode指令相依性分析...................20
3-3-2 Bytecode指令相依性改進...................21
3-3-3 程式記憶體使用率.........................24
3-4 系統架構...................................26
3-4-1系統硬體方塊..............................26
3-4-2 Answer to Reset..........................27
3-4-3 APDU協定.................................29
第四章 Java Card Microcontroller實作...........32
4-1 開發環境及相關工具.........................32
4-1-1 Verilog Design Flow......................32
4-1-2 Xilinx FPGA Design Flow..................34
4-2 系統時序模擬...............................35
4-2-1 SlookupSwitch時序........................35
4-2-2 Debit method時序.........................36
4-2-3 Credit method時序........................37
4-2-4 GetBalance method時序....................38
4-3 系統實現...................................40
4-3-1 Java Card Microcontroller架構............40
4-3-2 Java Card Microcontroller指令格式........41
4-3-3 Java Card Microcontroller旗標............43
4-3-4 Java Card Microcontroller指令運作........44
4-3-5 Java Card Microcontroller核心元件........46
4-3-6 Java Card Microcontroller程式記憶體......47
4-3-7 Java Card Microcontroller實體電路........48
第五章 測試與效能評估..........................49
5-1 Java Card Microcontroller之測試............49
5-2 系統效能評估...............................52
第六章 結論與未來工作..........................53
參考索引.......................................54
附錄一：縮寫名詞對照表.........................56
附錄二：指令運作說明...........................57
自述...........................................62

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