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研究生:王翊寧
研究生(外文):WANG, YI-NING
論文名稱:應用於高效能視訊編碼之頻寬有效率快速演算法設計
論文名稱(外文):Bandwidth-Efficient Fast Algorithm for High Efficiency Video Coding
指導教授:謝瑞鴻
指導教授(外文):HSIEH, JUI-HUNG
口試委員:洪金車黃有榕
口試委員(外文):HUNG, KING-CHU
口試日期:2018-07-20
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:79
中文關鍵詞:H.265H.264位元失真最佳化搜尋範圍移動估測頻寬
外文關鍵詞:HEVCH.264Motion EstimationBandwidthRDCost
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現今科技進步迅速,隨著行動通訊4G/LTE漸漸普及,帶動許多新媒體相關產業的發展,影音視訊的解析度與品質的需求也隨之提升,也因此視訊在做傳輸時所需要的頻寬與編碼壓縮時的資料量也越來越大,為了在有更好的壓縮效率下能夠保有視訊的質量,演算法固然會更加的複雜。在最新的視訊編碼標準H.265/High Efficiency Video Coding (HEVC)中,在編碼單元(Coding Unit, CU)上有了更加多元的模式,除了能夠對應不同解析度之外,也支援處理更高的解析度。對於行動裝置上的視訊影像,相對來說頻寬比較有限,所以對高解析度視訊降低頻寬的處理上會成為一個主要的目標。
本論文提出基於位元率失真最佳化(Rate-Distortion Optimization, RDO)的頻寬位元失真率最佳化(Bandwidth Rate-Distortion Optimization, BRDO)演算法;此演算法根據位元失真率成本(Rate-Distortion Cost, RDCost)之大小,來進行搜尋範圍(Search Range)的分類加以限制並降低頻寬的使用量,再搭配模擬兩種不同的搜尋演算法,全域搜尋(Full Search)和測試區域搜尋(Test Zone Search),不僅保持原有的影像品質及位元率之外,整體下來FS頻寬平均減少了46%左右,TZS頻寬平均減少了42%左右。
在硬體架構設計上是使用Synopsys(Verilog、Design Compiler、Verdi、Synthesis、PrimeTime®、PrimePower®)和Cell Library(TSMC 90nm CLN90G)實作,在最差的情況(Worst case)下仍然可以達到1.064 GHz,且功率消耗為0.9108 mW。

Thanks to the fast developing high technology nowadays, mobile telecommunication 4G/LTE is popularized worldwide, and which makes a rapidly growing New Media related Industry.With the higher requirement for good quality an-d high resolution of Video/Webcam , the bandwidth and the amount of coding compressed data for transmitting Video have to be expanded. In order to keep high performance of video under efficient data compression, more complicated mathematical calculations is a must.In the newest HEVC, CU is quite diversified in order to match different resolution requirement as well as to support higher resolution. Since the bandwidth of audio and video on mobile internet device is limited, our major target is to settle bandwidth problem on high resolution video, that is , to narrow the bandwidth.
This thesis puts forward the algorithm of Bandwidth-Rate-Distortion Optimization (BRDO), which is on basis of Rate-Distortion Optimization. The algorithm distributes bandwidth and search area by size of Rate-Distortion Cost (RDCost). It not only lowering the usage of bandwidth but maintaining quality and rate. On average, more than 56% of bandwidth's usages were saved and more than 60% of encoding time decrease largely.
The hardware architecture was implemented by using Synopsys (Verilog, Verdi, Design Compiler, Synthesis, PrimeTime®, PrimePower®) and Cell Library (TSMC 90nm CLN90G). The speed of our design was 1.1GHz under the worst case simulation case, and the power consumption was 0.873mW.

摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章 導論 1
1.1 簡介 1
1.2 研究目的與動機 2
1.3 論文章節安排 2
第二章 視訊編碼系統介紹 3
2.1 HEVC視訊編碼介紹 3
2.1.1 編碼單元(Coding Unit, CU) 5
2.1.2 預測單元(Prediction Unit, PU) 6
2.1.3 轉換單元(Transform Unit, TU) 8
2.1.4 階層式編碼架構 9
2.1.5 位元率失真最佳化(Rate-Distortion Optimization) 9
2.2 內嵌式迴圈濾波器(In-loop Filter) 14
2.3 量化(Quantization) 14
2.4 熵編碼(Entropy Coding) 15
2.4.1 適應性可變長度編碼(Context Adaptive Variable Length Coding , CAVLC) ………………………………………………………………………………………………………………………….…..16
2.4.2 適應性二進位算術編碼(Context Adaptive Binary Arithmetic, CABAC)….16
2.5 畫面內預測(Intra Predicition) 17
2.6 畫面間預測(Inter Predicition) 19
2.6.1 移動估測(Motion Estimation, ME)………………………………………………………….…19
2.6.2 移動向量預測(Motion Vetor Prediction, MVP)………………………………………….21
2.6.3 全域搜尋演算法(Full search Algorithm, FS)……………………………………………..24
2.6.4 測試區搜尋演算法(Test Zone Search Algorithm, TZS)……………………………..25
2.6.5 多幅參考畫面(Multi-Reference Frame)……………………………………………………..29
2.6.6 非整數點移動估測…………………………………………………………………………………….29
第三章 頻寬分配演算法架構設計 32
3.1 記憶體頻寬分析…………………………………………………………………………………………32
3.2 頻寬位元失真率最佳化(Bandwidth-Rate-Distortion Optimization, BRDO)演算法…………………………………………………………………………………………………………………………..……..34
3.2.1 移動向量預測與頻寬計算(MVP & BW Calculation) 41
3.2.2 頻寬位元失真率分布對應RDCost之分析 43
第四章 演算法實驗結果分析 47
4.1 H.264中時域與空間域的選擇…………………………………………………………………..52
4.2 H.265之演算法實現………………………………………………………………………………….54
第五章 硬體架構設計與結果驗證 64
5.1 Cell-based Design Flow………………………………………………………………………………64
5.2 演算法之硬體架構規劃…………………………………………………………………………….65
5.3 演算法之硬體內部設計…………………………………………………………………………….68
5.3.1 RDCost Classifier模組區塊 69
5.3.2 Threshold Selection模組區塊 70
5.3.3 Search Range Allocation模組區塊 71
5.4 硬體架構實驗數據…………………………………………………………………………………….72
5.5 實驗數據比較………………………………………………………………………………………….…75
第六章 結論及延伸討論 76
參考文獻 77

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