臺灣博碩士論文加值系統

本論文研製毫米波CMOS寬頻可變增益低雜訊放大器及使用前置失真線性器之94-GHz CMOS功率放大器，採用TSMC CMOS 0.18-μm製程或90-nm GUTM製程進行設計。12–25 GHz CMOS寬頻可變增益低雜訊放大器以電流控制機制(current steering)來控制電晶體轉導值使其主體電流產生變化以達增益之調控；寬頻設計的部份則利用電阻式回授的方式並加上額外之電感、電容來做為匹配網路。50–67 GHz CMOS寬頻可變增益放大器此架構的可變增益設計以及寬頻設計的部份與12–25 GHz CMOS寬頻可變增益低雜訊放大器設計類似，主要差異為:此寬頻放大器中額外使用了增益強化(gain boosting)電感來增加整體的增益表現，同時額外多使用一個輸出緩衝器(test buffer)來作為輸出端的寬頻匹配元件與提升增益之用。使用前置失真線性器之94-GHz CMOS功率放大器設計上採用串接四級common-source (CS)的cascode架構來提高增益輸出以減輕PA前端輸入電路的負擔，而為加強電路的線性度特性，此架構使用一線性器來強化IP1dB特性，同時級間匹配採用能達到較小面積的匹配網路以利系統整合。電路設計以Agilent ADS與Ansoft 3-D全波電磁模擬軟體HFSS進行模擬，量測部分則是採用on-wafer方式進行，根據欲量測特性之不同，相關量測方式亦有所調整。

This thesis presents the research on millimeter-wave (MMW) CMOS wideband variable-gain low-noise amplifiers (VG-LNAs) and a 94-GHz CMOS power amplifier (PA) with built-in pre-distortion linearizer, implemented by standard TSMC 0.18-μm or 90-nm GUTM CMOS process. To obtaine wideband frequency response, the resistive-feedback skill with additional passive components is used as the matching network. In the 60-GHz VG-LNA design, a gain boosting inductor is used in order to obtain a better gain performance. In 94-GHz CMOS PA design, a four stage CS cascade structure is adopted for output gain enhancement. Futhermore, the linearity performance of designed PA such as IP1dB is improved by the built-in pre-distortion linearizer. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.

第一章 緒論 1
1.1 研究動機與背景 1
1.2 論文架構 1

第二章 12–25 GHz CMOS寬頻可變增益低雜訊放大器 3
2.1 可變增益低雜訊放大器於系統應用之簡介 3
2.2 常見可變增益放大器及衰減器架構介紹 5
2.3 低雜訊放大器介紹 9
2.3.1多級電路系統雜訊指數 9
2.3.2 CMOS放大器雜訊來源 10
2.4常見之寬頻放大器設計 11
2.5 12–25 GHz CMOS寬頻可變增益放大器設計簡介 15
2.5.1 電路設計說明與考量 15
2.5.2設計流程總結 21
2.5.3模擬與量測結果 22
2.5.4 結果與討論 27

第三章 50–67 GHz CMOS寬頻可變增益低雜訊放大器 29
3.1 設計簡介 29
3.1.1 電路設計說明與考量 30
3.1.2設計流程總結 33
3.1.3 結果與討論 40

第四章 使用前置失真線性器之94-GHz CMOS功率放大器 43
4.1 功率放大器簡介 43
4.1.1 架構種類與重要參數 44
4.1.2驅動級線性度之設計考量 46
4.1.3匹配考量 47
4.1.4 穩定度考量 48
4.2 使用前置失真線性器之94-GHz CMOS功率放大器設計簡介 48
4.2.1電路設計說明與考量 49
4.2.2設計流程總結 53
4.2.3模擬與量測結果 55
4.2.4 結果與討論 58

第五章 結論 63

參考文獻 65

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