臺灣博碩士論文加值系統

在本篇碩士論文中，我們提出了低功率應用含垂直式雙閘極電流橋之無電容式動態隨機存取記憶體 (Vertical double gate transistor with n-bridge DRAM, VN-DRAM)。此VN-DRAM不像是傳統平面式電流橋架構只有一個閘極可以控制空乏區，我們提出的VN-DRAM擁有雙閘極來控制空乏區，因此在較短的閘極長度可以提升可程式規劃視窗(Programming Window (P.W.))。此外，此垂直架構之雙閘極在製程過程中是可以自我對準的。我們提出的VN-DRAM， 在元件寬度為45奈米跟閘極長度為11奈米的條件下，可程式規劃視窗可以達到  36 µA/µm。此架構擁有兩個P型區使資料延長保存時間 (Retention Time (R.T.))在常溫的時候可以增加到544 奈秒，在高溫358 K的時候可以達到72 奈秒。除此之外，VN-DRAM的最低的偏壓可以被操作在0.95伏特，在此操作偏壓下可以比在操作偏壓為1.2 伏特時減少40 %的功率消耗。我們在此提出操作偏壓微縮優異的新型架構，同時VN-DRAM寫入速度可以達到4 奈秒的快速操作。

In this thesis, we propose a Vertical double gate transistor with n-bridge DRAM (VN-DRAM) for low power applications. Unlike conventional current bridge architecture which has only one sided gate controllability of the depletion region, the proposed VN-DRAM has double gate control of the depletion region which enhances the programming window (P.W.) at shorter gate lengths. Also, the gate can be self-aligned. The proposed VN-DRAM achieves a P.W. of  36 µA/µm for device width of 45 nm at a gate length of 11 nm. VN-DRAM has two p-body regions which can store more holes, the retention time (R.T.) can be improved up to 544 ms at 300 K and 72 ms at 358 K. In addition, the lowest voltage for all operations of the proposed VN-DRAM can be limited to 0.95 V, it can reduce 40 % power consumption for Write ‘1’ operation compared to that of using power supply 1.2 V. Thus highlighting the voltage scalability of the proposed device. VN-DRAM has high speed operation which can reach 4 ns for Write ‘1’ operation.

中文審定書 i
英文審定書 ii
致謝 iii
摘要 iv
Abstract v
Contents vi
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 4
Chapter 2 Operation Principle 6
2.1 Physical Mechanism Discussion 6
2.2 Memory write mechanism 7
2.2.1 Gate Induced Drain Leakage (GIDL) 7
2.2.2 Impact Ionization (I.I.) 9
Chapter 3 Productions of Device 11
3.1 Process of Device 11
Chapter 4 Research Methods and Results Discussion 13
4.1 Physical Mechanism Model 13
4.2 Architecture Instructions 15
4.3 Operation Mode 19
4.4 I-V Characteristics 23
4.5 Programming Window 25
4.6 Data Retention Time 27
4.7 Write Time 30
4.8 Power Consumption 32
4.9 Disturbance Immunity 36
4.10 Scalability 38
4.11 1T-DRAM Benchmark 40
Chapter 5 Experimental Result and Explore 42
5.1 Design of Mask 42
Chapter 6 Conclusion and Future Work 44
6.1 Conclusion 44
6.2 Future Work 45
References 46
Appendix 55
Explore of Gate-All-Around structure 55
Experiment Measurement and Review 57

[1]G. E. Moore, “Craming more components onto integrated circuits,” IEEE Solid-State Circuits Society Newsletter, vol. 20, no. 3, pp. 33-35, Sept. 2006, doi: 10.1109/N-SSC.2006.4785860.
[2]C. Maleville, “Engineered substrates for Moore and more than Moore’s law: Device scaling: Entering the substrate era,” in Proc. IEEE SOI-3D-Subthreshold Microelectronics Tech. Unified Conf., pp. 1-5, Oct. 2015, doi: 10.1109/S3S.2015.7333494.
[3]K. Kim, C. G. Hwang, and J.-G. Lee, “DRAM technology perspective for gigabit era,” IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 598–608, Mar. 1998, doi: 10.1109/16.661221.
[4]H. P. Moll, J. Hartwich, A. Scholz, D. Temmler, A.P. Graham, S. Slesazek, G. Wedler, L. Heineck, T. Mono, U. Zimmermann, K. Schupke, F. Ludwig, I. Park, T. Tran, and W. Müller, “Self-alignment techniques to enable 40nm trench capacitor DRAM technologies with 3-D array transistor and single-sided strap,” IEEE VLSI Tech., pp. 188-189, Jun. 2007, doi: 10.1109/VLSIT.2007.4339687.
[5]H. Sunami, “The Role of the Trench Capacitor in DRAM Innovation,” IEEE Solid-State Circuits Newsl., vol. 13, no. 1, pp. 42–44, Dec. 2008, doi: 10.1109/N-SSC.2008.4785691.
[6]Y.-H. Wu, C.-M. Chang, C.-Y. Wang, C.-K. Kao, C.-M. Kuo, A. Ku, and T. Huang, “Augmented cell performance of NO-based storage dielectric by N2O-treated nitride film for trench DRAM,” IEEE Electron Device Lett., vol. 29, no. 2, pp. 149–151, Jan. 2008, doi: 10.1109/LED.2007.914082.
[7]C.-Y. Lee, C.-Y. Lee, C.-S. Lai, C.-M. Yang, and D.-H. L.Wang, “Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization,” IEEE Trans. Semicond. Manuf., vol. 25, no. 4, pp. 657–663, Jun. 2012, doi: 10.1109/TSM.2012.2206062.
[8]M. Kawano, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, and S. Matsui, “Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer,” IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1614–1620, Jun. 2008, doi: 10.1109/TED.2008.924068.
[9]J. Lim, H. Lim, and S. Kang, “3-D Stacked DRAM Refresh Management with Guaranteed Data Reliability,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 34, no. 9, pp. 1455–1466, Mar. 2015, doi: 10.1109/TCAD.2015.2413411.
[10]T. Nomura, R. Mori, K. Takayanagi, K. Fukuoka, and K. Nii, “Design Challenges in 3-D SoC Stacked With a 12.8GB/s TSV Wide I/O DRAM,” IEEE Journal On Emerging And Selected Topics In Circuits And Systems., vol. 6, no. 3, pp. 364–372, Apr. 2016, doi: 10.1109/JETCAS.2016.2547719.
[11]H.-J. Wann, and C. Hu, “A capacitorless DRAM cell on SOI substrate,” Proc. IEEE Int. Electron Devices Meet., pp. 635–638, Dec. 1993, doi: 10.1109/IEDM.1993.347280.
[12]S. Okhonin , M. Nagoga, J. M.Sallese, and P. Fazan, “A SOI capacitor-less 1T-DRAM concept,” in Proc. IEEE International SOI Conference, pp. 153-154, Oct. 2001, doi: 10.1109/SOIC.2001.958032.
[13]M. Aoulaiche, E. Simoen, C. Caillat, L. Witters, K. K. Bourdelle, B.-Y. Nguyen, J. Martino,C. Claeys, P. Fazan, and M. Jurczak, “Understanding and optimizing the floating body retention in FDSOI UTBOX,” Solid. State. Electron., vol. 117, pp. 123–129, May. 2016, doi: 10.1016/j.sse.2015.11.021.
[14]M. Sarajlić, and R. Ramović, “Analytical modeling of the triggering drain voltage at the onset of the kink effect for PD SOI NMOS,” in Proc. International Conference on Microelectronics, pp. 325-328, May. 2006, doi: 10.1109/ICMEL.2006.1650964.
[15]F. Gamiz, “Capacitor-less memory : advances and challenges,” in Proc. Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp. 68–71, Jan. 2016, doi: 10.1109/ULIS.2016.7440054.
[16]S. Cristoloveanu, and M. Bawedin, “FDSOI devices: Issues and innovative solutions,” in Proc. European Solid-State Device Research Conference, pp. 117-120, Sep. 2016, doi: 10.1109/ESSDERC.2016.7599602.
[17]H. ElDirani, M. Bawedin, K. Lee, M. Parihar, X. Mescot, P. Fonteneau, Ph. Galy, Gamiz, Y-T. Kim, P. Ferrari, and S. Cristoloveanu, “Competitive 1T-DRAM in 28 nm FDSOI Technology for Low-Power Embedded Memory,” in Proc. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 1-2, Oct. 2016, doi: 10.1109/S3S.2016.7804402.
[18]G. Kim, S. W. Kim, J. Y. Song, J. P. Kim, K.-C. Ryoo, J.-H. Oh, J. H. Park, H. W. Kim, and B.-G. Park, “Body-raised double-gate structure for 1T DRAM,” in Proc. Nanotechnology Materials and Devices Conference, pp. 259-263, Jun. 2009, doi: 10.1109/NMDC.2009.5167556.
[19]C.-C. Lin, J.-T. Lin, W.-H. Lee, C.-K. Huang, T.-C. Chang and A. Kranti, “Punch-Through Reading Mechanism and Body Raised up Structure for A Novel Punch-Through DRAM,” in Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 31–33, Oct. 2016, doi: 10.1109/ICSICT.2016.7999064.
[20]J.-T. Lin, P.-H. Lin, Y.-C. Eng, and Y.-R. Chen, “Novel vertical SOI-based 1T-DRAM with trench body structure,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1872–1877, May. 2013, doi: 10.1109/TED.2013.2259171.
[21]J.-T. Lin, and P.-H. Lin, “Multifunction behavior of a vertical MOSFET with trench body structure and new erase mechanism for use in 1T-DRAM,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3172–3178, Jul. 2014, doi: 10.1109/TED.2014.2336533.
[22]J.-S. Shin, H. Bae, J. Jang, D. Yun, J. Lee, E. Hong, D. H. Kim, and D. M. Kim, “A Novel Double HBT-Based Capacitorless 1T DRAM Cell With Si/SiGe Heterojunctions,” IEEE Electron Device Letters, vol. 32, no. 7, pp. 850-852, Feb. 2011, doi: 10.1109/LED.2011.2142390.
[23]J.-S. Shin, H. Choi, H. Bae, J. Jang, D. Yun, E. Hong, D. H. Kim, and D. M. Kim, “Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage,” IEEE Electron Device Letters, vol. 33, no. 2, pp. 134-136, Feb. 2012, doi: 10.1109/LED.2011.2174025.
[24]A. Pal, A. Nainani, and K. C. Saraswat, “Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain,” in Proc. International Conference on Simulation of Semiconductor Processes and Devices, pp. 376-379, Sep. 2013, doi: 10.1109/SISPAD.2013.6650653.
[25]A. Pal, A. Nainani, X. Bao, E. Sanchez, and K. C. Saraswat, “GaP Source - Drain SOI 1T - DRAM : Solving the Key Technological Challenges,” in Proc. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, vol. 33, no. 1, pp. 1-2, Feb. 2013, doi: 10.1109/S3S.2013.6716573.
[26]A. Biswas, and A. M. Ionescu, “Study of Fin-Tunnel FETs with doped pocket as Capacitor-less 1T DRAM,” in Proc. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf., pp. 1-2, Feb. 2014, doi: 10.1109/S3S.2014.7028203.
[27]N. Navlakha, J.-T. Lin, and A. Kranti, “Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism,” IEEE Electron Device Letters, vol. 37, no. 9, pp. 1127-1130, Sep. 2016, doi: 10.1109/LED.2016.2593700.
[28]N. Rodriguez, S. Cristoloveanu, and F. Gamiz, “A-RAM: Novel capacitor-less DRAM memory,” in Proc. IEEE Int. SOI Conf., pp. 1-2, Oct. 2009, doi: 10.1109/SOI.2009.5318734.
[29]N. Rodriguez, F. Gamiz, and S. Cristoloveanu, “A-RAM Memory Cell: Concept and Operation,” IEEE Electron Device Letters, vol. 31, no. 9, pp. 972-974, Sep. 2010, doi: 10.1109/LED.2010.2055531.
[30]N. Rodriguez, S. Cristoloveanu, and F. Gamiz, “Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible with Bulk and SOI Substrates,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2371-2377, Aug. 2011, doi: 10.1109/TED.2011.2147788.
[31]N. Rodriguez, C. Navarro, F. Gamiz, F. Andrieu, O. Faynot, and S. Cristoloveanu, “Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator,” IEEE Electron Device Letters, vol. 33, no. 12, pp. 1717-1719, Dec. 2012, doi: 10.1109/LED.2012.2221074.
[32]F. T. Wakam, J. Lacord, S. Martinie, F. T. Wakam, M. Bawedin, and S. Cristoloveanu, “Optimization guidelines of A2RAM cell performance through TCAD simulations,” in Proc. International Conference on Simulation of Semiconductor Processes and Devices, pp. 329–332, Sep. 2017, doi: 10.23919/SISPAD.2017.8085331.
[33]J.-H. Chen, S.-C. Wong, and Y.-H. Wang, “An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1400–1405, Jul. 2001, doi: 10.1109/16.930658.
[34]T. Tanaka, E. Yoshida, and T. Miyahit, “Scalability study on a capacitorless 1T-DRAM from single-gate PD-SOI to double-gate FinDRAM,” IEDM Tech. Dig. IEEE Int. Electron Devices Meet. 2004, pp. 919–922, Dec. 2004, doi: 10.1109/IEDM.2004.1419332.
[35]A. M. N. Lima, A. G. S. B. Neto, H. Neff, and E. U. K. Melcher, “Refined dielectric breakdown model for crystalline organic insulators: Electro-thermal instability coupled to interband impact ionization,” in Proc. IEEE International Power Modulator and High Voltage Conference, pp. 63–68, Aug. 2010, doi: 10.1109/IPMHVC.2010.5958296.
[36]Sentaurus Device User Guide, ver. K-2015.06, Synopsys, Inc., Mountain View, CA, USA, Jun. 2015.
[37]J. Schmidt, and A. Cuevas, “Electronic properties of light-induced recombination centers in boron-doped Czochralski silicon,” J. Appl. Phys., vol. 86, no. 6, pp. 3175–3180, May. 1999, doi: 10.1063/1.371186.
[38]The International Technology Roadmap for Semiconductors 2.0, 2015.
[39]Z. Huo, S. Baik, S. Kim, I. Yeo, U. Chung, and J. T. Moon, “Sub-6F2 charge trap dynamic random access memory using a novel operation scheme,” in Proc. 2006 64th Device Research Conf., pp. 261–262, Jun. 2006, doi: 10.1109/DRC.2006.305173.
[40]P. Saha, S. Basak, and S. K. Sarkar, “Performance Analysis of a High Speed, Energy Efficient 4x4 Dynamic RAM Cell Array using 32nm fully depleted SOI/SON, and CNFET,” 2014 Recent Advances in Engineering and Computational Sciences, pp. 1–6, Mar. 2014, doi: 10.1109/RAECS.2014.6799532.
[41]J.-T. Lin, H.-H. Lin, Y.-J. Chen, C.-Y. Yu, A. Kranti, C.-C. Lin, and W.-H. Lee, “Vertical Transistor with n-Bridge and Body on Gate for Low-Power 1T-DRAM Application,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 4937–4945, Nov. 2017, doi: 10.1109/TED.2017.2766563.
[42]Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors,” 2014 ACM/IEEE 41st International Symposium on Computer Architecture, pp. 361–372, Jun. 2014, doi: 10.1109/ISCA.2014.6853210.
[43]R. Ritzenthaler, T. Schram, E. Bury, J. Mitard, L. Ragnarsson, and G. Groeseneken, “Low-power DRAM-compatible Replacement Gate High-k / Metal Gate Stacks,” in Proc. 2012 Proceedings of the European Solid-State Device Research Conference, pp. 242–245, Sep. 2012, doi: 10.1109/ESSDERC.2012.6343378.
[44]Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi, and T. Hiramoto, “Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications,” 2015 Symposium on VLSI Technology, pp. T170–T171, Jun. 2015, doi: 10.1109/VLSIT.2015.7223665.
[45]A. Lahgere, and M. J. Kumar, “1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS,” IEEE Trans. Electron Devices, vol. 64, no. 4, pp. 1583–1590, Feb. 2017, doi: 10.1109/TED.2017.2669096.