臺灣博碩士論文加值系統

本研究成功開發出可拉伸式的有機/無機混成薄膜應用於電晶體/記憶體，以PEDOT：PSS作為閘極，藉由溶膠凝膠法合成出可溶性聚醯亞胺(Polyimide)，再將聚醯亞胺與二氧化矽-二氧化鈦混成為有機/無機混成薄膜，改變無機物的重量百分比，來找出最佳化的條件。另外添加了Jeffamine D2000與Polyurethane於有機/無機混成薄膜中，藉此增加元件的拉伸性質，提高元件對於拉伸的承受能力；此外，為了實現在新興材料的應用，將以PffBT4T-2OD作為半導體層材料，以及銦镓液態合金(E-GaIn)作為上電極，期許元件能有更好的特性。
電性質分析中在無機物含量為30wt%時遷移率可達到0.189cm2/V*S，開關電流比為1.38*104 ；有添加Jeffamine D2000在無機物含量為30wt%時遷移率可達到0.689cm2/V*S以及開關電流比為8.53*104 ；有添加Polyurethane在無機物含量為30wt%時遷移率可達到0.433cm2/V*S以及開關電流比為5.32*104 。添加Jeffamine D2000 於介電複合薄膜後元件會使薄膜機械性質提高，並不會影響電性，在元件整體拉伸後電性質還能維持；而添加Polyurethane可以讓元件拉伸比例至50%、拉伸次數到達150次。

In this study, a stretchable organic/inorganic hybrid film was successfully developed for transistor/memory.PEDOT:PSS was used as a gate and synthesize soluble polyimide by sol-gel method. Polyimide is mixed with silicon-titanium dioxide to form an organic/inorganic hybrid film, and the weight percentage of the inorganic substance is changed to find an optimum condition. In addition, Jeffamine D2000 and Polyurethane are added to the organic/inorganic hybrid film to increase the tensile properties of the component and improve the tensile resistance of the component. In order to realize the application in emerging materials, PffBT4T-2OD will be used as the semiconductor. As well as the indium gallium liquid alloy (E-GaIn) as the upper electrode, expects the component to have better characteristics.
In the electrical property analysis, the mobility can reach 0.189cm2/V*S and the switching current ratio is 1.38*104 at an inorganic content of 30wt%; the addition of Jeffamine D2000 has a mobility of 0.689 cm 2 /V*S and a switching current ratio of 8.53*104 at an inorganic content of 30 wt%; the addition of Polyurethane has a mobility of 0.433 cm 2 /V*S and a switching current ratio of 5.32*104 at an inorganic content of 30wt%. Adding Jeffamine D2000 to the dielectric composite film will improve the mechanical properties of the film without affecting the electrical properties. The electrical properties can be maintained after the component is stretched as a whole. Adding Polyurethane allows the component to stretch to 50%； the number of stretches reached 150 times.

目錄
明志科技大學碩士學位論文指導教授推薦書 I
明志科技大學碩士學位論文口試委員審定書 II
誌謝 III
摘要 IV
ABSTRACT V
目錄 VI
圖目錄 VIII
表目錄 XIV
第一章 緒論 1
1-1.前言 1
1-2. 研究動機與目的 2
第二章 文獻回顧與整理 3
2-1.有機材料 – 聚亞醯胺 3
2-2.無機材料 – 二氧化矽、二氧化鈦 3
2-3.有機無機奈米混成混成材料 5
2-4.有機半導體層材料 5
2-5.電極材料 7
2-6.電晶體型記憶體應用 8
2-7.拉伸式有機薄膜電晶體 9
2-8.重要的有機電晶體參數 9
第三章：實驗藥品、儀器及方法 14
3-1. 實驗藥品 14
3-2. 實驗儀器 17
3-2-1.製程儀器 17
3-2-2.分析儀器 19
3-3. 實驗方法 20
3-3-1.結構分析 20
3-3-2.表面型態分析 21
3-3-3光學性質分析 21
3-3-4電性質分析 22
3-3-5熱性質分析 22
3-3-6. 溶液製備 23
3-3-7.元件(OTFT)製備 27
第四章：結果與討論 30
4-1. POLYIMIDE/ TIO2-SIO2、POLYIMIDE/ TIO2-SIO2 / JEFFAMINE D2000與POLYIMIDE/ TIO2-SIO2/POLYURETHANE奈米粒子混成薄膜 30
4-1-1.結構分析 30
4-1-2.熱分析 31
4-1-3.光學性質分析 32
4-1-4.薄膜表面分析 33
4-1-5. 介電性質分析 36
4-2.PFFBT4T-2OD為半導體層應用於元件性質 38
4-2-1.混成薄膜之OTFT元件電性質分析 38
4-2-2混成薄膜之OTFT元件電性質分析記憶體性質分析 48
第五章：結論 69
第六章：參考文獻 71

圖目錄
圖2-1、亞醯胺基結構 3
圖2-2、(a) rutile、(b) Anatase(c) brookite、二氧化鈦結晶結構晶系圖 5
圖2-3、MOSFET的轉移特性曲線 13
圖3-1、配置PEDOT:PSS溶液之流程圖 23
圖3-2、合成有機材料Polyimide實驗流程圖 24
圖3-3、合成無機材料 TiO2-SiO2實驗流程圖 25
圖 3-4、Jeffamine D2000 化學結構 25
圖 3-5、Polyurethane 化學結構 26
圖 3-6、Polyimide/ TiO2-SiO2無機奈米粒子、Polyimide/ TiO2-SiO2無機奈米粒子/Jeffamine D2000與Polyimide/ TiO2-SiO2無機奈米粒子/ Polyurethane 混成溶液實驗流程圖 27
圖3-7、元件結構示意圖 29
圖4-1、(a) PST0~PST40(b)PST0D~PST40D(c) PST0U~PST40U混成材料之FTIR光譜圖 31
圖4-2、(a) PST0~PST40(b)PST0D~PST40D(c) PST0U~PST40U混成材料之TGA曲線(Nitrogen) 32
圖4-3、(a) PST0~PST40(b)PST0D~PST40D(c) PST0U~PST40U混成材料之DSC曲線圖 32
圖4-4、(a) PST0~PST40(b)PST0D~PST40D(c) PST0U~PST40U混成材料之UV光譜圖 33
圖4-5、PST0-PST40混成材料之AFM圖 33
圖4-6、PST0D-PST40D混成材料之AFM圖 34
圖4-7、PST0U-PST40U混成材料之AFM圖 34
圖4-8、PST0-PST40、PST0D-PST40D與PST0U-PST40U混成材料之介電常數圖(在10kH頻率下) 36
圖4-9、(a) PST0~PST40(b)PST0D~PST40D(c) PST0U~PST40U混成薄膜之漏電流曲線圖 37
圖 4-10OTFT結構示意圖 38
圖4-11、PST0-PST40、PST0D-PST40D與PST0U-PST40U混成薄膜OTFT元件之output曲線圖 39
圖4-12、PST0~PST40混成薄膜OTFT元件之I-V曲線圖 40
圖4-13、PST0D~PST40D混成薄膜OTFT元件之I-V曲線圖 40
圖4-14、PST0U~PST40U混成薄膜OTFT元件之I-V曲線圖 41
圖4-15、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸一次之I-V曲線圖 41
圖4-16、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸十次之I-V曲線圖 42
圖4-17、PST0D、PST0U、PST30、PST30D與PST30U混成薄膜OTFT元件以5%拉伸二十次之I-V曲線圖 42
圖4-18、PST0D、PST0U、PST30、PST30D與PST30U混成薄膜OTFT元件以5%拉伸五十次之I-V曲線圖 43
圖4-19、PST0U與PST30U混成薄膜OTFT元件以5%拉伸一百次之I-V曲線圖 43
圖4-20、PST0UD與PST30U混成薄膜OTFT元件以5%拉伸一百五十次之I-V曲線圖 44
圖4-21、 PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸一次之I-V曲線圖 44
圖4-22、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸十次之I-V曲線圖 44
圖4-23、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸二十次之I-V曲線圖 45
圖4-24、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸五十次之I-V曲線圖 45
圖4-25、PST0U與PST30U混成薄膜OTFT元件以10%拉伸一百次之I-V曲線圖 46
圖4-26、PST0U與PST30U混成薄膜OTFT元件以20%拉伸一次之I-V曲線圖 46
圖4-27、PST0U與PST30U混成薄膜OTFT元件以20%拉伸十次之I-V曲線圖 47
圖4-28、PST0U與PST30U混成薄膜OTFT元件以20%拉伸二十次之I-V曲線圖 47
圖4-29、PST0U與PST30U混成薄膜OTFT元件以20%拉伸五十次之I-V曲線圖 47
圖4-30、PST0U與PST30U混成薄膜OTFT元件以50%拉伸一次之I-V曲線圖 48
4-2-2混成薄膜之OTFT元件電性質分析記憶體性質分析 48
圖4-31、PST0~PST40混成薄膜OTFT元件之WRER記憶體特性 分析圖 48
圖4-32、PST0D~PST40D混成薄膜OTFT元件之WRER記憶體特性分析圖 49
圖4-33、PST0U~PST40U混成薄膜OTFT元件之WRER記憶體特性分析圖 50
圖4-34、 PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸一次之WRER記憶體特性分析圖 50
圖4-35、 PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸十次之WRER記憶體特性分析圖 50
圖4-36、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸二十次之WRER記憶體特性分析圖 51
圖4-37、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸五十次之WRER記憶體特性分析圖 52
圖4-38、PST0U與PST30U混成薄膜OTFT元件以5%拉伸一百次之WRER記憶體特性分析圖 52
圖4-39、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸一百五十次之WRER記憶體特性分析圖 53
圖4-40、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸一次之WRER記憶體特性分析圖 53
圖4-41、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸十次之WRER記憶體特性分析圖 53
圖4-42、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸二十次之WRER記憶體特性分析圖 54
圖4-43、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸五十次之WRER記憶體特性分析圖 54
圖4-44、PST0U與PST30U混成薄膜OTFT元件以10%拉伸一百次之WRER記憶體特性分析圖 55
圖4-45、PST0U與PST30U混成薄膜OTFT元件以20%拉伸一次之WRER記憶體特性分析圖 55
圖4-46、PST0U與PST30U混成薄膜OTFT元件以20%拉伸十次之WRER記憶體特性分析圖 55
圖4-47、PST0U與PST30U混成薄膜OTFT元件以20%拉伸二十次之WRER記憶體特性分析圖 56
圖4-48、PST0U與PST30U混成薄膜OTFT元件以20%拉伸五十次之WRER記憶體特性分析圖 56
圖4-49、PST0U與PST30U混成薄膜OTFT元件以50%拉伸一次之WRER記憶體特性分析圖 56
圖4-50、PST0~PST40混成薄膜OTFT元件之持續時間記憶體特性分析圖 57
圖4-51、PST0D~PST40D混成薄膜OTFT元件之持續時間記憶體 特性分析圖 58
圖4-52、PST0U~PST40U混成薄膜OTFT元件之持續時間記憶體 特性分析圖 58
圖4-53、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸一次之持續時間記憶體特性分析圖 59
圖4-54、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸十次之持續時間記憶體特性分析圖 59
圖4-55、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸二十次之持續時間記憶體特性分析圖 60
圖4-56、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以5%拉伸五十次之持續時間記憶體特性分析圖 60
圖4-57、PST0U與PST30U混成薄膜OTFT元件以5%拉伸一百次之持續時間記憶體特性分析圖 61
圖4-58、PST0U與PST30U混成薄膜OTFT元件以5%拉伸一百五十次之持續時間記憶體特性分析圖 61
圖4-59、PST0、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸一次之持續時間記憶體特性分析圖 62
圖4-60、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸十次之持續時間記憶體特性分析圖 62
圖4-61、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸二十次之持續時間記憶體特性分析圖 62
圖4-62、PST0D、PST0U、PST30D與PST30U混成薄膜OTFT元件以10%拉伸五十次之持續時間記憶體特性分析圖 63
圖4-63、PST0U與PST30U混成薄膜OTFT元件以10%拉伸一百次之持續時間記憶體特性分析圖 63
圖4-64、PST0U與PST30U混成薄膜OTFT元件以20%拉伸一次之持續時間記憶體特性分析圖 64
圖4-65、PST0U與PST30U混成薄膜OTFT元件以20%拉伸十次之持續時間記憶體特性分析圖 64
圖4-66、PST0U與PST30U混成薄膜OTFT元件以20%拉伸二十次之持續時間記憶體特性分析圖 64
圖4-67、PST0U與PST30U混成薄膜OTFT元件以20%拉伸五十次之持續時間記憶體特性分析圖 65
圖4-68、PST0U與PST30U混成薄膜OTFT元件以50%拉伸一次之持續時間記憶體特性分析圖 65
圖4-69、PST0、PST0D、PST0U、PST30D與PST30U拉伸前的 I-V圖 67
圖4-70、PST0、PST0D、PST0U、PST30D與PST30U遷移率對 於拉伸比例的趨勢圖 68
圖4-71、PST0、PST0D、PST0U、PST30D與PST30U遷移率對 於拉伸次數的趨勢圖 68

 

表目錄

表3-1、 Polyimide/ TiO2-SiO2配方 28
表3-2、Polyimide/ TiO2-SiO2/Jeffamine D2000配方 28
表3-3、Polyimide/ TiO2-SiO2/Polyurethane配方 28
表4-1、PST0-PST40、PST0D-PST40D與PST0U-PST40U混成材料性質檢測之分析表 35
表4-2、PST0-PST40、PST0D-PST40D與PST0U-PST40U混成材料介電性質之分 37
表4-3、PST0-PST40、PST0D-PST40D與PST0U-PST40U混成薄膜之遷移率及開關比 65
表4-4、PST0、PST0D與PST0U混成薄膜在不同拉伸比例以及不同拉次數下的遷移率及開關比 66
表4-5、PST30、PST30D與PST30U混成薄膜在不同拉伸比例以及不同拉次數下的遷移率及開關比 66

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