臺灣博碩士論文加值系統

在現今，直流對直流降壓轉換器廣泛的應用在各種電子電路中，而我設計的直流降壓轉換器，是使用數位的控制方式，並且使用數位脈波寬度調變器，來調變電壓。
而本論文採用的是以計數器為基礎的脈波寬度調變器，具有高解析度及較低的硬體成本。
本論文的數位式直流降壓轉換器，是由降壓轉換器的基本架構以及數位脈波寬度調變器所組成的。數位脈波寬度調變器實現於FPGA開發版，並且與直流降壓轉換器的PCB板做整合及量測。然後將數位脈波寬度調變器以台積電180nm的製程並且使用Cell-Based Design flow的設計方式去做下線晶片的動作，最後再與直流降壓轉換器的PCB板做整合及量測。最後實驗量測結果顯示，我可將輸入電壓1.8伏特~3.3伏特降到0.8伏特~2.5伏特。當操作於輸入電壓為3.3伏特與輸出電壓為1.8伏特的條件下，我的輸出漣波電壓為80毫伏特以及轉換效率為89.5%。

In today's DC-DC buck converter is widely used in a variety of electronic circuits, and I designed the DC buck converter is the use of digital control, and the use of digital pulse width modulator to modulate the voltage. This paper presents a counter-based digital pulse width modulator with high resolution and low hardware costs.
The digital DC buck converter in this thesis is composed of the basic structure of the buck converter and digital pulse width modulator. I implemented the digital pulse width modulator in the FPGA development board and integrated it with the PCB of the DC buck converter. Then the digital pulse width modulator to TSMC 180nm process and the use of Cell-Based Design flow design approach to tape-out. Finally, with the PCB of the DC buck converter integration and measurement. The final experimental measurements show that I can drop the input voltage from 1.8V~ 3V to 0.8V~ 2.5V. When operating at 3.3V input voltage and 1.8V output voltage, output ripple voltage is no higher than 100 millivolts and the conversion efficiency can reach 89.5%.

Table of Contents
致謝詞………………………..……………………………..………i
摘要…………………………………………………………….….ii
Abstract…………………………………………………..………iii
Table of Contents………………………....……………...……….v
List of Tables………………..…………...……….…...…..……..viii
List of Figures…………………...……….……………...…..……ix
Chapter 1 Introduction………...…………………………………1
1.1 Background and Motivation……………………………….……………...1
1.2 Thesis Organization………………………………………….....................3
Chapter 2 Introduction of DC-DC Buck Converter…………….4
2.1 Regulator types introduced………………………. ……………………….4
2.2 Low Dropout Linear Regulator…………………. ……………………….4
2.3 Working principle of DC-DC Buck Converter………….……………….6
2.4 Definition of DC-DC Buck Converter characteristic parameters…….……9
2.4.1 Line Regulation……………………………………….………………....9
2.4.2 Load Regulation……………………………………….……………….10
2.4.3 Transient Load Response…………………………….………………...10
2.4.4 Output Ripple Voltage……………………………….…………………12
2.4.5 Power Conversion Efficiency………………………….……………….13
Chapter 3 Circuit structure of traditional DC-DC Buck Converter………………………………………………14
3.1.1 Voltage Control Mode……………………………………………….....14
3.1.2 Current Control Mode………………………………………………..17
3.2 Traditional Digital Buck Converter……………………………….19
3.2.1 Time-Based PID Compensator for Buck Converter………………….21
3.3 Digital pulse width modulator……………………………………….22
3.3.1 Counter-Based DPWM…………………………………………….23
3.3.2 Delay-Line DPWM……………………………………………….24
3.3.3 Hybrid DPWM………………………………………………….26
Chapter 4 Circuit Design of Digitally Controlled DC-DC Buck Converter………………………………………………28
4.1 Design concept and circuit architecture………………………………...28
4.2 Circuit Structure and Working Principle of New Digital Pulse Width Modulation Controller………………………………………………………29
4.3 New Digital Pulse Width Modulator Sub-Circuit Introduction…...……..31
4.3.1 Phase Detector………………………………………………………...31
4.3.2 Finite State Machine…………………………………………………...33
4.3.3 8-bit UP Counter……………………………………………………...34
4.3.4 8-bit Comparator……………………………………………………...35
4.3.5 SR Latch……………………………………………………………...36
Chapter 5 New Buck Converter using FPGA implementation and measurement…………………………37
5.1 Introduction……………………………………………………………...37
5.2 Field-Programmable Gate Array introduction………………...…………38
5.3 Buck Converter Circuit board....................................................................39
5.3.1 SI4724………………………………………………...…………….…40
5.3.2 Voltage Controlled Oscillator (TLC2933A)…………………………...40
5.3.3 Passive Components (Inductors/Capacitors)…………………………...40
5.4 Buck Converter simulation…....................................................................40
5.5 New digital buck converter measurement results.......................................42
Chapter 6 New Buck Converter using Cell-Based Design Flow implementation and measurement ……………………………48
6.1. Introduction…………………………………………………………...48
6.1.1 Cell-Based Design Flow……………………………………………...48
6.2 Implement for DC-DC Buck Converter……………………………...54
6.3 Measurement of DC-DC Buck Converter……………………………...56
6.3.1 Testing setup…………………………………………………………...57
6.4 Simulation Result………………………………………………………...60
6.5 Measurement Result……………………………………………………62
References……………………………….………………………..64

List of Tables
Table 2.1 Regulator comparison table……………….……………………………..….….4
Table 3.1 Comparison of Voltage Control Mode and Current Control Mode……………19
Table 3.2 Comparison of Counter-Based DPWM and Delay-Line DPWM………...……26
Table 5.1 Buck Converter Board Specifications………...……………………………..…42
Table 5.2 Digital Buck Converter Performance Specifications…………………..………46
Table 6.1 EDA tools for cell based design flow……………………………………..……53

List of Figures
Fig. 1.1 Smart phone power management block diagram………………….……………....2
Fig. 2.1 Low dropout Linear Regulator……………...………….….….………………….. 5
Fig. 2.2 Synchronous Buck converter………………...………….….….………………….. 6
Fig. 2.3 Buck Converter………………….……..…………………...………………………8
Fig. 2.4 Synchronous Buck Converter Transient Response, (a) Equivalent circuit for load current variation, (b) Load current variation versus output voltage………………………..11
Fig. 2.5 Buck converter output ripple voltage………………………………………...……12
Fig. 3.1 DC-DC Buck Converter control block diagram……………………………...….14
Fig. 3.2 A conventional Voltage Control Mode Buck Converter circuit architecture, (a) Circuit architecture, (b) The duty cycle waveform….......................................................….16
Fig. 3.3 A conventional Current Control Mode Buck Converter circuit architecture, (a) Circuit Architecture, (b) The duty cycle waveform…...………………………………….18
Fig. 3.4 Traditional Digital Control Buck Converter Architecture……………………...….20
Fig. 3.5 Time-based compensator Buck Converter , (a) Circuit architecture, (b) Timing diagram………………………………………………………………………………...….22
Fig. 3.6 Counter-Based DPWM (a) Circuit Architecture (b) Timing Diagram……….…....24
Fig. 3.7 Delay-Line DPWM, (a) Circuit Architecture, (b) Timing Diagram…………….25
Fig. 3.8 Hybrid DPWM , (a) Circuit Architecture, (b) Timing Diagram………………….27
Fig. 4.1 New digital Buck Converter Architecture………………………………………...28
Fig. 4.2 Circuit Architecture of New Digital Pulse Width Modulator……………………...29
Fig. 4.21 New digital step-down converter circuit flow chart……………………………...30
Fig. 4.3.1 Phase Detector, (a) Circuit Architecture, (b) Timing Diagram…………………32
Fig. 4.3.11 Phase Detector simulation waveform………………………………..…………33
Fig. 4.3.2 State picture of Finite State Machine………………………………..…………33
Fig. 4.3.21 Finite State Machine simulation waveform………………………..…………33
Fig. 4.3.3 8-bit UP Counter simulation waveform………………………..…………34
Fig. 4.3.4 8-bit Comparator simulation waveform………………………..…………35
Fig. 4.3.5 SR Latch simulation waveform………………………………..…………36
Fig. 5.1 New Digital Buck Converter Circuit Architecture……………………..…………37
Fig. 5.2 Altera DE2 FPGA Development kit…………………………………..…………38
Fig. 5.3 Buck Converter circuit board…………………………………………..…………39
Fig. 5.4 Netlist of DPWM circuit…………………………………………..…………41
Fig. 5.5 DPWM Simulation, (a) Duty=25%, (b) Duty=50%, (c) Duty=75%………………41
Fig. 5.6 Digital Buck Converter Measurement Environment…………………..…………43
Fig. 5.7 Measurement result 3.3v to 1.8v, Duty=55%…………………………..…………44
Fig. 5.8 DPWM Measurement result, (a) Duty=25%, (b) Duty=50%, (c) Duty=75%, (d) Duty=80%……………………………………………………………………..…………46
Fig. 6.1.1 Cell-Based Design flow of digital circuit design……………………..…………49
Fig. 6.1.2 RTL Level Design Flow……………………………………………..…………50
Fig. 6.1.3 From RTL to Gate-level Using Logic Synthesis……………………..…………51
Fig. 6.1.4 From Pre-layout Gate-level Netlist to Layout………………………..…………52
Fig. 6.1.5 Auto Placement & Route Flow……………………………………..…………52
Fig. 6.2.1 Layout of DPWM…………………………………………………..…………55
Fig. 6.2.2 Wire bonding SB18 for DPWM……………………………………..…………55
Fig. 6.2.3 The actual picture of the chip………………………………………..…………56
Fig. 6.3.1 Automatic Test Equipment Testing flow……………………………..…………57
Fig. 6.3.2 AdvantestV93000 PS1600…………………………………………..…………58
Fig. 6.3.3 The procedure of test flow…………………………………………..…………58
Fig. 6.4.1 Post-Layout simulation……………………………………………..…………61
Fig. 6.4.2 Post-Layout simulation……………………………………………..…………61
Fig. 6.5.1 Measurement result, (a), (b)…………………………………………..…………62

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