臺灣博碩士論文加值系統

在目前的IC製程中，金氧半場效電晶體(MOSFET)為了避免短通道效應，其介電層的厚度也越來越薄，導致更大的漏電流及可靠度問題，因此使用高介電係數材料為不可避免的趨勢。在高介電係數材料中，含有鉿（Hf）成分的材料被認為極有應用的潛力。而過去研究指出，添加氧氣進行沉積後退火，能修補介電層中的氧缺陷，使元件在偏壓不穩定性之可靠度測試能有所改善，但卻極少有探討添加氧氣退火對二氧化鉿介電層之熱載子效應及基本電性的影響，因此，我們將針對此方面做一探討。
實驗元件是聯華電子所提供45奈米製程的n型電晶體（nMOSFET），二氧化鉿介電層的製作方式是由原子層沉積技術完成。實驗考慮的參數，包括改變電壓、溫度以及不同通道長度等，再依據所得資料，進行統計、分析實驗結果與電壓及溫度的關係，且探討有無添加氧氣進行沉績後退火之間的差異。
研究結果顯示，添加氧氣進行沉積後退火，對於二氧化鉿介電層在基本電性分析上，並沒有較大差異的改善，其相似的電容-電壓曲線，使得等效氧化層厚度也雷同。而在CHC的加壓測試條件下，短通道(0.1μm)元件劣化程度明顯比長通道(10μm)嚴重，且依據實驗數據及分析，添加氧氣進行退火之n型電晶體元件，經由添加氧氣於退火製程，臨界電壓偏移量及汲極電流劣化量能有效降低，進而改善元件劣化程度。

In order to avoid the short channel effect in the MOSFET, the thickness of the dielectric has gradually become thinner. However, the serious problems of leakage current and reliability due to the thinning oxide are also unavoidable. Therefore, using high-k materials passes into one of the most significant studies. After many years of researches, the Hafnium-based high-k materials emerge as the most promising candidates to replace SiO2 and SiON gate dielectrics. It has been reported that the oxygen vacancy defects of high-k dielectrics can be passivated by annealing process, and the device degradation of bias temperature instability (BTI) tests can be improved. However, the hot carrier injection (HCI) is still an important reliability issue. And only few literatures concerned about the channel hot carrier reliability for adding oxygen in post-deposition annealing. Hence, this study is concentrated on this subject.
The nMOSEFT experimental samples were fabricated from 45 nm node high performance logic technology of UMC. The process of HfO2 dielectric layer was deposited by atomic layer deposition (ALD). The wafers were then annealed with and without oxygen after ALD. The channel width of the nMOSFETs is 10 μm and channel lengths are 10 μm and 0.1 μm. In this research, the different stress voltages and temperatures are included in the experiment. Consequently experimental data are used to figure out the dependence of degradation on stress voltage and temperature, and to determine the difference of two kinds of wafers.
The experimental results show that the basic electric characteristics have no significant improvement for the process with oxygen post-deposition annealing. After the CHC stress, the degradation in those short channel nMOSFETs reveals larger than that in long channel. The threshold voltage shift becomes larger as stress voltage and temperature increasing. From the analyzed data, the process with oxygen post-deposition annealing can effectively reduce the degradation of the devices; it should be due to the passivation of oxygen vacancies during the oxygen annealing.

Contents
Abstract (Chinese) …………………………………………………………………….i
Abstract (English)…………………………………………………………………….iii
Acknowledgement……………………………………………………………………iv
Contents ……………………………………………………………………………...vi
List of Tables………………………………………………………………………....vii
List of Figure………………………………………………………………………...viii
Chapter 1 INTRODUCTION………………………………………………………..1
1.1 Background……………………………………………………………………...1
1.2 Thesis Organization……………………………………………………………. .2
Chapter 2 ELECTRICAL AND HOT CARRIER CHARACTERISTICS OF HIGH-K GATE DIELECTRICS…………………………………………3
2.1 From SiO2 to High-κ Gate Dielectrics…………………………………………..3
2.2 Research about Hf-based Dielectrics……………………………………………5
2.2.1 Properties of HfO2 gate dielectrics……………………………………….…5
2.2.2 The higher density of defects in Hf-based dielectrics………………………6
2.2.3 The effect of different postdeposition annealing condition with HfO2 dielectrics………………………………………………………………….7
2.3 Research about HCE of High-κ Dielectrics……………………………………11
2.3.1 Introduction of hot carrier effect (HCE) ………………………………….11
2.3.2 Physical mechanism for HCE…………………………………………..…11
2.3.2.1 Channel hot electron (CHE) injection………………………………....11
2.3.2.2 Drain avalanche hot carrier (DAHC) injection………………………..13
2.3.3 Hot carrier effect of high-κ dielectrics……………………………………14
2.4 Research about The Effect of Oxygen Postdeposition Annealing on Reliability Issues of HfO2 nMOSFETs.…………………………………………………....19
2.5 Problem Formulation.………………………………………………………….27
Chapter 3 EXPERIMENTS.……………………………………………………….29
3.1 Experimental Procedures.……………………………………………………..29
3.2 Stress Conditions and Measurement Conditions.………………………..……30
3.3 Experimental Structures Process.……………………………………………..31
Chapter 4 RESULTS AND DISCUSSION.……………………………………….33
4.1 nMOSFET with Gate Dielectric on Different PDA.………………………….33
4.1.1 Electrical characteristics of nMOSFET with HfO2 gate dielectrics……...33
4.1.1.1 Id-Vd characteristics.…………………………………………………33
4.1.1.2 Id-Vg characteristics.………………………………………………....34
4.1.1.3 C-V characteristics.…………………………………………………..35
4.1.2 Channel hot carrier (CHC) stress of different PDA conditions………...…36
4.1.2.1 The Vt shift and Id degradation of the CHC stress with different PDA conditions at 25℃…………………………………………………….36
4.1.2.2 The Vt shift and Id degradation of the CHC stress with different PDA conditions at 55℃…………………………………………………….38
4.1.2.3 The Vt shift and Id degradation of the CHC stress with different PDA conditions at 85℃…………………………………………………….39
4.1.3 For short channel devices, the CHC stress of different PDA conditions ...40
4.1.4 The Vt shift depended on temperatures with different PDA conditions ….42
4.1.5 Summary of the Vt shift with different channel lengths ………………….45
4.2 The Variation of Interface States and Oxide Trap after CHC stress …………..47
4.3 The CHC Degradation Models Charges ………………………………………50
4.4 Lifetime Prediction …………………………………………………………....54
Chapter 5 CONCLUSIONS AND FUTURE WORK …………………………….57
5.1 Conclusions …………………………………………………………………...57
5.2 Future Work …………………………………………………………………...58
REFERENCES ……………………………………………………………………....59

References
[1]M. Jo, H. Park, J.-M. Lee et al., “Effect of oxygen postdeposition annealing on bias temperature instability of hafnium silicate MOSFET,” IEEE Electron Device Lett., vol. 29, no. 4, pp. 399-401, 2008.
[2]Kerber, E. Cartier, L. Pantisano et al., “Characterization of the VT -instability in SiO2/HfO2 gate dielectrics,” Proc. IRPS, pp.41-45, 2003.
[3]S. Zafar, A. Kumar, E. Gusev et al., “Threshold voltage instabilities in high-κ gate dielectric stack,” IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45–64, Mar. 2005.
[4]H. Park, R. Choi, B. H. Lee et al., “Decoupling of cold-carrier effects in hot-carrier reliability assessment of HfO2 gated nMOSFETs,” IEEE Electron Device Lett., vol. 27, no. 8, pp. 662–664, Aug. 2006.
[5]N. A. Chowdhury, D. Misra, “Charge Trapping at Deep States in Hf–Silicate Based High-Gate Dielectrics,” Journal of The Electrochemical Society, 2007.
[6]J. Robertson, “Interfaces and defects of high-k oxides on silicon,” Solid-State Electronics, pp. 283-293, 2005.
[7]C.-W. Hsu, Y.-K. Fang, W.-K. Yeh et al., “Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing,” Microelectronics Reliability, vol. 50, pp. 618–621, 2010.
[8]A. Chin, Y .H. Wu, S.B. Chen et al., ”High quality La203 and A1203 gate dielectrics with equivalent oxide thickness 5-10 Å,’’ VLSI Tech. Dig., pp. 16, 2000.
[9]W. J. Qi, R. Nieh, B. H. Lee et al., “MOSCAP and MOSFET characteristics using Zr02 gate dielectric deposited directly on Si,” IEDM Tech. Dig., pp.145, 1999.
[10]I. Crupi, “Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate,” Microelectronic Engineering, vol. 86, pp. 1–3, 2009.
[11]J. Robertson, “Electronic structure and band offsets of high dielectric constant gate oxides,” Mater. Research Soc., vol. 27, pp. 217-221, 2002.
[12]J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. B, vol. 18, pp. 1785-1791, 2000.
[13]G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[14]Y. S. Lin, R. Puthenkovilakam and J. P. Chang, “Dielectric property and thermal stability of HfO2 on silicon,” Appl. Phys. Lett., vol. 81, pp. 2041-2043, 2002.
[15]L. Kang, B. H. Lee, W. J. Qi et al., “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Lett., vol. 21, pp. 181-183, 2000.
[16]J. Robertson, “Interfaces and defects of high-K oxides on silicon,” Solid-State Electronics, vol. 49, pp. 283–293, 2005.
[17]M. Koyama, A. Kaneko, T. Ino et al., “Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics,” in IEEE IEDM Tech. Dig., pp. 849–852, 2002.
[18]M. S. Akbar, H.-J. Cho, R. Choi et al., “Optimized NH3 annealing Process for high-quality HfSiON gate oxide,” IEEE Electron Device Lett., vol. 25, pp. 465–467, 2004.
[19]J. C. Wang, Y. P. Hung, C. L. Lee et al.,“Improved Characteristics of Ultrathin CeO2 by Using Postnitridation Annealing,” J. Electrochem. Soc., vol. 151, pp. F17-F21, 2004.
[20]Y. Nishikawa, T. Yamaguchi, M. Yoshiki et al., “Interfacial properties of single-crystalline CeO2 high-k gate dielectrics directly grown on Si (111),” Appl. Phys. Lett., vol. 81, pp.4386-4388, 2002.
[21]K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, pp. 2757-2776, 1996.
[22]G. D. Wilk, R. M. Wallace and J. M. Anthony, High-k gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys. vo1. 89, no. 10, May 2001.
[23]Q. Lu, H. Takeuchi, R. Lin et al., “Hot Carrier Reliability of n-MOSFET with Ultra-thin Hf02 Gate Dielectric and Poly-Si Gate,” IEEE 40th Annual International Reliability Physics Symposium. Dallas, 2002
[24]G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[25]B. H. Lee, L. Kang, W. J. Qi et al., “Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application,” in IEEE IEDM Tech. Dig., pp. 133-136, 1999.
[26]E. P. Gusev, D. A. Buchanan, E. Cartier et al., “Ultrathin high-K gate stacks for advanced CMOS devices,” in IEEE IEDM Tech. Dig., pp. 451-454, 2001.
[27]J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. B, vol. 18, pp. 1785-1791, 2000.
[28]H. Iwai, S. Ohmi, S. Akama et al., “Advanced gate dielectric materials for sub-100 nm CMOS,” in IEEE IEDM Tech. Dig., pp. 625-628, 2002.
[29]L. Kang, B. H. Lee, W. J. Qi et al., “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Lett., vol. 21, pp. 181-183, 2000.
[30]B. H. Lee, R. Choi, L. Kang et al., “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8Å-12Å),” in IEEE IEDM Tech. Dig., pp. 39-42, 2000.
[31]D. Barlage, R. Arghavani, G. Dewey et al., “High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics,” in IEEE IEDM Tech. Dig., pp. 231-234B, 2001.
[32]H. Park, M. Hasan, M. Jo et al., “ Metal Gate and High-k Gate Dielectrics for sub 50 nm High Performance MOSFETs,” Electronic Materials Letters, Vol. 3, No. 2, pp. 75-85, 2007.
[33]H. Park, M. Jo, H. Choi et al., “The Effect of Nanoscale Nonuniformity of Oxygen Vacancy on Electrical and Reliability Characteristics of HfO2 MOSFET Devices,” IEEE Electron Device Lett., vol. 29, NO. 1, pp. 54-56, JANUARY 2008.
[34]H. Takeuchi, D. Ha, and T.-J. King, “Observation of bulk HfO2 defects by spectroscopic ellipsometry,” J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 22, no. 4, pp. 1337–1341, Jul. 2004.
[35]J. J. Sanchez and T. A. DeMassa, “Review of Carrier Injection in the Silicon/Silicon-Dioxide System,” IEEE Proceeding-G, vol. 138, p.379,1991.
[36]T. H. Ning, “Hot-carrier emission currents in N-channel IGFETs,” IEDM Tech. Dig., p.144, 1977.
[37]P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Characterization of electronic gate current in IGFET’s operating in the linear and saturation regions,” IEEE Trans. Electron Devices, vol. ED-24, p. 1200, 1977.
[38]C. Hu, C. T. Simon, H. Fu-Chieh et al., “Hot-electron-induced MOSFET degradation--Model, monitor, and improvement,” IEEE Transactions on Electron Devices, vol. 32, pp. 375-385, 1985.
[39]K. R. Hofmann, C. Werner, W. Weber et al., “Hot electron and hole-emission effects in short n-channel MOSFET''s, ” Electron Devices, IEEE Transactions on, vol. 32, pp. 691-699, 1985.
[40]E. Amat, T. Kauerauf, R. Degraeve et al., “Channel Hot-Carrier degradation under static stress in short channel transistors with high-k/metal gate stacks,” IEEE, pp. 103-106, 2008.
[41]J.H. Sim, B. H. Lee, R. Choi et al., “Hot Carrier Degradation of HfSiON Gate Dielectrics With TiN Electrode,” IEEE Transactions on Devices and Materials Reliability, vol. 5, no. 2, JUNE 2005.
[42]K. Takeuchi et al., “0.15 μm CMOS with high reliability and performance,” in IEDM Tech. Dig., p. 883, 1993.
[43]M. Jo, H. Park, M. ChangR et al., “Oxygen vacancy induced charge trapping and positive bias temperature instability in HfO2 nMOSFET,” Microelectronic Engineering, vol. 84, pp. 1934–1937, 2007.
[44]J. H. Stathis and D. J. DiMaria,” Reliability projection for ultra-thin oxides at low voltage,” IEDM Tech. Dig., pp. 167, 1998.
[45]S. Y. Chen, C. H. Tu, J. C. Lin et al., “Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs,” IIRW Final Report, pp.163-166, 2006.