臺灣博碩士論文加值系統

本論文設計兩個偽隨機位元序列產生器及三級環型電壓控制振盪器，晶片採用台積電0.18 µm CMOS製程技術設計。我們設計序列長度為27-1的偽隨機位元序列產生器，並整合內建時脈訊號，且以電流模式邏輯的電路結構，可提升電路操作速度。
第一個偽隨機位元序列產生器採用線性回授位移暫存結構電路，操作速度為3-Gbps，功率消耗為221.639 mW，晶片面積為566.795×557.63 µm2。第二個偽隨機位元序列產生器採用並列結構，可同時產生八個2-Gbps偽隨機位元序列，或可再利用多工器組成4-Gbps的偽隨機位元序列，功率消耗為472.35 mW，晶片面積為1196.31×1010.795µm2。
此偽隨機位元序列產生器電路除可做為高速資料訊號誤碼及訊號品質測試之訊號源外;我們也探討應用於抖動容忍度的測試;以及也可做為多通道或多階調變測試的訊號源。

In this thesis, two pseudo-random bit sequence (PRBS) generators and a three-stage ring voltage control oscillator were designed in TSMC 0.18mm complementary metal-oxide-semiconductor (CMOS) process. The sequence length of the PRBS generators with built-in clock was designed as 27-1. Using current-mode logic (CML) circuit structure, the PRBS generators can be operated at higher rate.
The first PRBS generator used a linear feedback shift register structure, the operation rate of the circuit is 3-Gbps, the power consumption is 221.639 mW, and the chip area is 566.795×557.63 μm2. The second PRBS generator used a parallel architecture, and the circuit can output simultaneous eight 2-Gbps PRBS signals or a 4-Gbps PRBS signal through a multiplexer. The power consumption of the second PRBS generator is 472.35 mW, and the chip area is 1196.31×1010.795 μm2.
Our PRBS generator can be applied in bit-error rate and signal quality tests as a testing signal source. Using our PRBS generator, the jitter tolerance test was also investigated. The PRBS generator will become a signal source for multi-channel or multi-level modulation transmission test.

摘要 I
Abstract II
目錄 IV
表目錄 VII
圖目錄 VIII
第一章緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 相關文獻探討 4
1.4 論文架構 7
第二章電路結構與訊號原理分析 8
2.1振盪器原理介紹 8
2.2 電流模式邏輯 9
2.3 偽隨機位元序列產生器基本原理 12
2.4 眼圖量測分析 14
2.5 抖動容限 16
2.6 IC設計流程 19
第三章內建時脈之偽隨機位元序列產生器 21
3.1電壓控制振盪器參數介紹 21
3.2環型電壓控制振盪器電路架構 24
3.3環型電壓控制振盪器電路模擬結果 26
3.3.1 環型電壓控制振盪器電路前模擬 26
3.3.2 環型電壓控制振盪器電路後模擬 29
3.3.3 環型電壓控制振盪器電路量測 32
3.4 討論 35
3.5 偽隨機位元序列產生器與電壓控制振盪器整合電路 37
3.5.1 環型電壓控制振盪器電路前模擬 41
3.5.2 環型電壓控制振盪器電路後模擬 44
3.5.3偽隨機位元序列產生器與電壓控制振盪器整合電路前模擬 48
3.5.4偽隨機位元序列產生器與電壓控制振盪器整合電路後模擬 50
3.5.5 晶片量測 57
3.6討論 61
第四章內建時脈之並列式偽隨機位元序列產生器 62
4.1並列式內建時脈之偽隨機位元序列產生器架構 63
4.2並列式內建時脈之偽隨機位元序列產生器模擬 67
4.2.1電路前模擬結果 67
4.2.2電路後模擬結果 72
4.3討論 80
第五章結論 82
5.1研究重點整理 82
5.2未來展望 85
參考文獻 86

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