臺灣博碩士論文加值系統

隨著晶片系統設計變的龐大，設計負責特定功能且可重用的矽智財(Intellectual Property Cores)產品來加速晶片設計的生意逐漸增加，但伴隨矽智財的商機增長，盜取矽智財的案例也逐漸上升，因此在矽智財保護的設計研究中使用浮水印(watermarks)阻止矽智財被竊取是一件很重要的問題。先前的研究顯示，增加浮水印的個數可以使矽智財保護的安全性以及差異性提高。且在高階合成階段利用矽智財輸出端暫時關閉的時間(Temporally Free)設計浮水印已經被提出作為有效且低額外設計消耗的方法，透過研究此設計方法的過程中，我們發現可以利用高階合成中的空閒功能單元(Idle Functional Units)進一步的增加浮水印的個數。在本篇文章中，我們提出在高階合成階段利用空閒功能單元最大化浮水印數量的設計方法，我們的方法是以啟發式(Heuristic)演算法方法在額外資源的設計條件考量下，利用空閒功能單元將浮水印的數量最大化，比起既有的浮水印設計研究，我們可以達到更多的浮水印數量，並且不會產生過多的額外資源負擔。

To cope with the increasing design complexity, the companies reuse more and more intellectual property cores to accelerate integrated circuit design. As the number of intellectual properties core is growing, the cases of intellectual property core theft are also on the rise. The protection of intellectual property core by inserting watermarks during the integrated circuit design is a very important issue.
Previous works have shown that more number of intellectual property watermarks can let intellectual property cores to achieve high security and difference. In the high-level synthesis process, to utilize the temporally free output slots (in the operating stage) to produce watermarks is recognized as a useful technique for protecting intellectual property cores. In this thesis, we point out that the utilization of the idle functional units can increase the number of watermarks. Based on this observation, we propose an effective approach to increase the number of watermarking technique based on the utilization of idle functional units in the high level synthesis process. Our objective is to maximize the number of watermarks under the overhead constraint. Experimental results show that our approach achieves very good results.

目錄
中文摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 1
1.1 研究背景 2
1.2 研究目的 5
1.3 全文架構 6
第二章 基本概念 7
2.1 高階合成階段的設計概念 7
2.2 高階合成的資料路徑圖 11
2.3 高階合成階段的浮水印設計研究 14
第三章 研究動機 18
3.1 空閒功能單元的介紹 18
3.2 以空閒功能單元增加浮水印個數的方法 19
第四章 利用空閒功能單元最大化浮水印數量演算法 22
4.1 整體的浮水印設計流程 22
4.2 空閒功能單元分析與資料路徑圖的建造 23
4.3在增加額外設計架構限制下進行空閒功能單元挑選 27
4.4演算法複雜度分析 28
第五章 實驗結果與分析 29
5.1 實驗硬體與軟體平台 29
5.2 測試電路 29
5.3 實驗流程與方法 30
5.4 實驗結果與分析 32
第六章 結論 34
參考文獻 35
附錄一 口試委員問答 39

圖目錄
圖1.1 以合成階段區分下的三種浮水印設計方案 3
圖2.1.1 資料流程圖1 8
圖2.1.2 兩種不同限制要求下的資料流程圖 10
圖2.2.1 加入內部運算過程資料與功能單元元件資訊的資料流程圖 11
圖2.2.2 四個暫存器資源限制下的資料路徑與資料儲存狀態圖 13
圖2.2.3 三個暫存器資源限制下的資料路徑與資料儲存狀態圖 13
圖2.3.1 資料流程圖2 14
圖2.3.2 兩個輸出端的輸出情形 15
圖2.3.3 資料路徑與資料儲存狀態圖 15
圖2.3.4 加入浮水印設計的資料路徑圖 16
圖2.3.4 加入浮水印設計後的兩個輸出端的輸出情形 16
圖3.1.1 資料流程圖與功能單元使用情況 18
圖3.2.1 加入空閒功能單元產生更多的子浮水印印記 19
圖3.2.2 加入空閒功能單元應用下的資料路徑與資料儲存狀態圖 20
圖4.1.1 整體設計流程圖 22
圖4.2.1 整體分析空閒功能單元與資料路徑圖虛擬碼 23
圖4.2.2 分析功能單元的可進行額外利用的操作步驟 25
圖4.2.3 分析暫存器資料可取代的操作步驟 25
圖4.2.4 分析暫存器與功能單元的資料路徑關係 26
圖4.2.5 分析功能單元與輸出、輸入端的資料路徑關係 26
圖4.3.1 在增加額外設計架構限制下進行空閒功能單元挑選 27
圖5.3.1 實驗流程圖 31

表目錄
表2.3.1 計算浮水印可能性個數公式中使用的變數 17
表5.2.1 測試電路之電路特性 30
表5.3.1 各測試電路的資源分配 31
表5.4.1 在不增加額外設計架構下浮水印個數比較實驗結果 33

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