臺灣博碩士論文加值系統

本論文探討十二位元之連續漸進式(SAR)類比數位轉換器(ADC)的設計與實現。這個ADC架構主要是以連續漸進式類比數位轉換器為基礎，為了提升取樣的操作速度，搭配使用次階式(Subrange)架構運作。另外，本論文提出新的動態邏輯電路來減少比較器輸出至數位轉換器(DAC)切換開關的延遲時間，可以減少整體ADC的轉換時間。為了滿足十二位元的線性度要求，在數位類比轉換器(DAC)中，使用二元式窗切換技術以及電容交換技術，可以得到更好的線性度。
在台積電的65奈米製程下，我們實現兩個連續漸進式類比數位轉換器。第一個ADC是一個十二位元每秒一億次取樣之連續漸進式類比數位轉換器，其晶片面積是0.048平方毫米。在1.2伏特操作電壓以及100MHz取樣頻率下，功耗是1.8毫瓦。量測到的動態效能，有效位元(ENOB)為9.65 bits；訊噪失真比(SNDR)為59.84 dB；無雜散動態範圍(SFDR)為67.18 dB。在使用電容交換技術之後，無雜散動態範圍(SFDR)提升到80.74dB。靜態效能量測：微分非線性誤差(DNL)為+1.47/-0.72 LSB；積分非線性誤差(INL)為+4.01/-0.7 LSB。第二個ADC是一個十二位元每秒兩億五千萬次取樣之連續漸進式類比數位轉換器，其晶片大小為0.124平方毫米。在1.2伏特的操作電壓及250MHz的取樣頻率下，模擬結果的動態效能為，訊噪失真比(SNDR)為64 dB，無雜散動態範圍(SFDR)為82.7 dB。

This thesis is aimed to present 12-bit Sub-ranged successive approximation register (SAR) analog-to-digital converters (ADCs). In order to speed up the sampling rate, the ADC architecture is proposed using the subrange SAR operation. Besides, by applying a new dynamic latch logic architecture, the DAC control delay between the comparator output and DAC switch is reduced. Thus, the sampling rate of the ADC is also improved. To achieve the 12-bit linearity requirement, the binary-window and capacitor-swapping switching techniques are applied in the DAC.
Two ADCs were implemented in TSMC 65 nm digital CMOS process. The first one is a 12-bit 100-MS/s ADC, which occupies an active area of 0.048 mm^2 . At 100-MS/s, the ADC consumes a total power of 1.8 mW from a 1.2V supply. The measured ENOB is 9.65 bits. Without the capacitor swapping scheme, the measured SNDR and SFDR are 59.84dB and 67.18dB, respectively. After using the swapping scheme, the SFDR is improved to 80.74dB. The measured DNL is+1.47/-0.72 LSB and the INL is +4.01/-0.7 LSB. The other one is a 12-bit 250-MS/s ADC which occupies an active area of 0.124 mm^2 . Using a 1.2V supply and a 250 MHz sampling rate, the measured SNDR and SFDR are 64dB and 82.7dB, respectively.

目錄
摘 要 I
Abstract II
致 謝 III
目錄 V
圖目錄 VIII
表目錄 XII
第一章 緒論 1
1-1 研究動機與目的 1
1-2 章節說明 3
第二章 文獻回顧 4
2-1 管線式類比數位轉換器 4
2-2 連續漸進式類比數位轉換器 8
2-3 混合式類比數位轉換器 12
2-3-1 管線連續漸進式類比數位轉換器 12
2-3-2 次階連續漸進式類比數位轉換器 14
2-4 結論 19
第三章 次階連續漸進式類比數位轉換器的架構考量 20
3-1 次階連續漸進式類比數位轉換器架構 20
3-2 次階連續漸進式類比數位轉換器時序分析 24
3-3 次階連續漸進式類比數位轉換器的非線性誤差 26
3-3-1 數位類比轉換器增益誤差 26
3-3-2 取樣相異誤差 29
3-3-3 比較器偏移誤差 32
第四章 十二位元次階連續漸進式類比數位轉換器之晶片實現 34
4-1 十二位元次階連續漸進式類比數位轉換器之架構 34
4-2 取樣電路 38
4-3 比較器 42
4-3-1 粗略類比數位轉換器之比較器 42
4-3-2 精準類比數位轉換器之比較器 44
4-3-3 比較器偏移校正技術 45
4-4 數位類比轉換器 49
4-4-1 交換式電容技術 49
4-4-2 二元視窗切換技術 52
4-4-3 數位類比轉換器的切換 54
4-4-4 數位類比轉換器電容陣列設計 58
4-5 邏輯控制電路 62
4-5-1 自操作迴圈 62
4-5-2 動態閂鎖數位類比轉換器控制 63
4-6 佈局考量 69
4-7 模擬結果 71
4-8 量測結果 72
4-8-1 實驗設定 72
4-8-2 動態效能 74
4-8-3 靜態效能 77
4-8-4 電容交換技術效能 78
4-8-5 實驗結果分析 80
4-9 結論 88
第五章 十二位元每秒兩億五千萬次取樣類比數位轉換器之晶片實現 90
5-1 乒乓類比數位轉換器架構 90
5-2 乒乓取樣電路架構 92
5-3 比較器之改善 94
5-4 偏移校正技術之改善 95
5-5 模擬結果 96
5-6 佈局考量 98
第六章 結論與未來展望 99
6-1 結論 99
6-2 未來展望 101
參考文獻 102

[1] Y.-C. Huang and T.-C. Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques,” IEEE Trans. Circuits Syst. I, vol. 58, no. 6, pp. 1157–1166, June, 2011.
[2] J. Chu, L. Brooks, and H.-S. Lee, " A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration, " Symp. on VLSI Circuits Dig. Tech. Papers, Jun. 2010.
[3] B. Hershberg, et al., “Ring Ampiflier for Switched-Capacitor Circuits,” ISSCC Dig. Tech. Papers, pp. 460-461, Feb. 2012.
[4] ] J. Kim and B. Murmann, "A 12-bit, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration," IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2141-2151, Sep. 2012.
[5] H.-H. Boo, D.-S. Boning, and H.-S. Lee, “A 12b 250MS/s Pipelined ADC with Virtual Ground Reference Buffers,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 1-3.
[6] Y. Lim and M. P. Flynn, “A 100 MS/s 10.5 b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers,” in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 202-203.
[7] Jorge Lagos, et al, “A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS,” 2017 Symp. on VLSI Circuits, 2017, pp. 1-2.
[8] C.-C Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, and C.-H. Huang, “A 10b 100MS/s 1.13mW SAR ADC with binary scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, pp.386–387, Feb. 2010.
[9] J.-P. Mathew, L. Kong, and B. Razavi, “A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V Supply,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2015, pp. 66-67.
[10] D. Luu et al., “A 12b 61dB SNDR 300MS/s SAR ADC with inverterbased preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET,” in 2017 Symposium on VLSI Circuits, Jun 2017.
[11] M. Inerfield, et al., “An 11.5-ENOB 100-MS/s 8mW Dual-Reference SAR ADC in 28nm CMOS,” IEEE Symp. VLSI Circuits, pp. 192-193, June 2014.
[12] Chun C. Lee, et al., “A SAR-Assisted Two-Stage Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859-869, Apr. 2011.
[13] H. Huang, S. Sarkar, B. Elies, and Y. Chiu, “28.4 a 12b 330ms/s pipelined-sar adc with pvt-stabilized dynamic amplifier achieving lt;1db sndr variation,” in 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 472–473, Feb 2017.
[14] K. Yoshioka, T. Sugimoto, N. Waki, S. Kim, D. Kurose, H. Ishii, M. Furuta and A. Sai, “ A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique , ” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Mar. 2017, pp. 478–479.
[15] Y. Lim, and M. P. Flynn, “A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SARassisted pipeline ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2017.
[16] Y.-H. Chung and C.-W. Yen, “ An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS, ” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 25, No. 12, pp. 3434 -- 3443, Aug. 2017.
[17] C.-C. Liu, “A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2016, pp. 462–463.
[18] Z. Zhang, W.-C Yu and G.-J Xie, “ A 10-bit 100-MS/s hybrid ADC based on flash-SAR architecture ,” IEEE Int. Conf. on Solid-State and Integrated Circuit Tech. Papers, Aug. 2016, pp. 725-727.
[19] R. Kapusta, J. Shen, S. Decker, H. Li, and E. Ibaragi, “A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS, ISSCC, session 26, 2013.
[20] W.-H. Tseng, W.-L. Lee, C.-Y. Huang, and P.-C. Chiu, “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE J. Solid-State Circuits, vol. 51, no. 10, pp. 2222-2231, Jul. 2016.
[21] W. Liu, P. Huang, and Y. Chiu, “A 12 b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” in IEEE ISSCC Dig. Tech. Paper, Feb. 2010, pp. 380–381.
[22] Y.-H. Chung, M.-H. Wu, and H.-S. Li, “A 12-bit 8.47-fJ/conversion-step capacitor-swapping SAR ADC in 110-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 10–18, Jan. 2015.
[23] Y.-H. Chung, C.-W. Yen, and M.-H. Wu, “A 24-μW 12-b 1-MS/s SAR ADC with two-step decision DAC switching in 110-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 11, pp. 3334–3344, Nov. 2016.
[24] Y.-H. Chung, C.-W. Yen, and P.-K. Tsai, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme,” Int. J. Circuit Theory Appl., vol. 46, no. 4, pp. 748–763, Apr. 2018.
[25] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched-opamp circuits,” IEE Electron. Lett., vol. 35, pp. 8-10, Jan. 1999.
[26] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," in IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004.
[27] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self- calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2008, pp. 269–272.
[28] S. W. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, 2006.
[29] Liu, C.C., Chang, S.J., Huang, G.Y., and Lin, Y.Z.: “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure“, IEEE J. Solid-State Circuits, 2010, 45, (4), pp. 731–740.
[30] Y.-S. Hu, C.-H. Shih, H.-T. Tai, H.-W. Chen, H.-S. Chen , “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40-nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2014, pp. 81.
[31] B.P. Ginsburg, and A.P. Chandrakasan, “500-MS/s 5-bit ADC in 65nm CMOS with split capacitor array,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.
[32] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tsai, “A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386–387.
[33] Y.-H. Chung, W.-S. Rih, and C.-W. Chang , “ A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55nm CMOS ,”accepted by TCAS-II.
[34] J. Luo, J. Li, N. Ning, Y. Liu and Q. Yu, “ A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS ,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. PP, no. 99, pp. 1–9, Jul. 2018.
[35] S. H. Lewis, “Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications,” IEEE Trans. Circuits Syst. II, vol. 39, no. 8, pp. 516–523, Aug. 1992.
[36] Y. S. Hu, et al, "A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), KaoHsiung, 2014, pp. 81-84.