臺灣博碩士論文加值系統

遵守摩爾定律驅使積體電路持續不斷提高電路密度；透過三維堆疊技術已是電子封裝之趨勢，其中利用矽穿孔(through silicon via, TSV)使得晶片間能垂直互連更為其關鍵技術。然而，TSV結構中多個材料間熱膨脹係數的差異，另外會造成不匹配問題，產生熱應力，從而發生TSV銅凸與脫層等結構問題，另外從過去的研究中，也發現熱應力對矽晶格有壓阻效應，影響載子移動速率和影響晶片之性能及可靠度。
本研究為了瞭解TSV在熱製程下之應力分布等情況，透過有限元素法對TSV進行模擬取得應力，並利用壓阻效應計算其對n-MOS與p-MOS之影響。藉改變TSV中結構之幾何尺寸，如TSV直徑、TSV深寬比、介電層厚度與TSV間距等，模擬TSV之應力，透過壓阻效應公式，計算並分析MOS於矽晶格方向[100]與[110]時，其載子移動率變化程度與觀察排除區(keep-out-zone, KOZ)所涉及之範圍。最後，利用田口分析方法對陣列式TSV進行優化設計，以減少排除區影響範圍，並使的晶片之體積尺寸大幅縮小。

Moore's Law drives the integrated circuit to continuously increase its circuit density for which 3D stacking technology is essential by the technology of through silicon via (TSV). TSV provides vertical interconnections between stacking dies. However, due to thermal stresses induced by the mismatch of coefficients of thermal expansion (CTE) between the related materials for TSV, structure reliability problems occur such as copper via pumping and interfacial delamination. Previous studies indicate that the induced thermal stress could lead to a piezoresistive effect on silicon which in turn causes undesirable carrier mobility in the device and affects the performance and reliability of the produced chip.
In this study, a finite element method was adopted to investigate the stress distribution of TSV under thermal process to examine possible piezoresistive effects TSV on the n-MOS and p-MOS structure by changing the geometry of the structure of TSV, including TSV diameter, TSV aspect ratio, dielectric layer thickness and TSV pitches. The piezoresistive effect of MOS in the silicon lattice directions [100] and [110] was studied for carrier mobility change to determine the range of keep-out zone (KOZ). Taguchi method was used to further optimize the array TSVs to reduce the KOZ range. The results show that the sizes of KOZ of the chip can be significantly reduced to increase the distribution density of TSV of the chip.

口試委員會審定書 #
摘要 i
EXTENDED ABSTRACT ii
誌謝 vi
目錄 vii
表目錄 x
圖目錄 xii
第一章 緒論 1
1.1 前言 1
1.2 研究動機與目的 4
1.3 文獻回顧 5
1.4 論文架構 7
第二章 基礎技術與理論 8
2.1 TSV概述 8
2.1.1 TSV技術與結構 8
2.1.2 TSV製造製程概述 9
2.2 壓阻效應 11
2.2.1 單晶矽之壓阻效應原理[35] 11
2.2.2 單晶矽之壓阻效應值[36; 37] 13
2.3 分析軟體介紹 14
2.3.1 熱分析原理[38] 15
2.3.2 熱-結構耦合分析原理 16
2.4 田口方法介紹[39] 17
2.4.1 直交表 18
2.4.2 信號雜訊比 18
2.4.3 因子反應表與反應圖 19
2.4.4 變異分析 19
第三章 有限元素分析 22
3.1 有限元素模擬規劃 22
3.2 有限元素模擬設定[40] 23
3.2.1 定義TSV之材料性質 23
3.2.2 建立有限元素模型 24
3.2.3 切割網格 26
3.2.4 定義邊界條件 28
第四章 結果與討論 29
4.1 TSV結構之模擬分析 29
4.1.1 矽晶格材料性質模擬比較 29
4.1.2 排除區分析 33
4.2 第一階段模擬 35
4.2.1 一次一因子模擬選擇 35
4.2.2 一次一因子模擬結果 36
4.3 第二階段模擬 48
4.3.1 田口方法模擬設計 48
4.3.2 田口方法實驗結果 50
第五章 結論與建議 67
5.1 結論 67
5.2 建議 69
參考文獻 70

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