臺灣博碩士論文加值系統

本論文採用tsmcTM 0.18-µm、tsmcTM 90-nm與WINTM 0.25-µm GaN製程設計五顆功率放大器，電路設計上選擇操作於X頻段與Ka頻段，藉由模擬不同製程之電晶體特性，選出最佳之電晶體大小與操作電流密度，結合變壓器形成寬頻匹配與運用多蒂特性使電路效率增加，最後量測電路特性以驗證電路設計之結果。
第一顆與第二顆皆為採用磁耦合變壓器於Ka頻段之90-nm CMOS寬頻功率放大器，此電路為兩級共源級結合中性化電路之設計，輸出與輸入採用磁耦合巴倫器，級間匹配則採用磁耦合變壓器增加電路頻寬，另外，於第二顆設計中加入了預匹配的考量，得以縮小晶片面積與增加頻寬，傳輸增益分別為17.43、14.5 dB，飽和輸出功率分別為14.73 、18.4 dBm，1-dB 增益壓縮點輸出功率分別為10.7、14.5 dBm，晶片面積分別為0.73 (1.41 × 0.405) mm2與0.67 (1.01 × 0.67) mm2。
第三顆使用0.18-m CMOS製程於X頻段之功率放大器，此功率放大器為採用中性化架構之兩級電路再結合A類並聯B類特性，增加電路的1-dB 增益壓縮點輸出功率與效率，輸出端與輸入端皆使用磁耦合巴倫器，級間匹配使用T型匹配增加電路頻寬，傳輸增益為20.1 dB，飽和輸出功率為20.1 dBm，1-dB 增益壓縮點輸出功率為18.4 dBm，加入A類並聯B類電晶體後，改善了最高輸出功率3.8 dBm與功率附加效率3.4%，晶片面積為1.78 (1.95 × 1.13) mm2。
第四顆為0.25-m GaN製程於X頻帶之二元功率結合功率放大器，電路採用兩級共源級架構，輸出端採用兩路並聯以增加輸出功率加上低阻抗結合器減少功率損耗，傳輸增益為16.35 dB，飽和輸出功率分別為33.2 dBm，1-dB 增益壓縮點輸出功率為24.5 dBm，晶片面積分別為3.47 (1.98 × 1.75) mm2。
第五顆為0.25-m GaN製程於X頻帶之多蒂功率放大器，輸出端採用T型匹配取代四分之一波長以縮小面積，輸入端則採用藍基耦合器，傳輸增益為11.8 dB，飽和輸出功率分別為35.9 dBm，功率回退附加效率為39.9 %，功率附加效率最高為41.5 %，晶片面積分別為3.03 (1.73 × 1.75) mm2。

The thesis developed five power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WINTM 0.25-µm GaN for both X-band and Ka-band operations. The best transistor size and biasing current density of the used transistors were chosen by simulating in different processes. The wideband matching was realized by the magnetically coupling transformer and the enhanced efficiency was realized by using Doherty architecture. Finally, the circuit performance was verified by the measuring small and large signal parameters, such as S-parameters, output power, linearity and modulated signals, etc.,
The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for X-band operation. This two-stage power amplifier adopted the unilateralization technique which was constructed by a class A amplifier in parallel with class B one to increase the overall output 1-dB compression power (OP1dB) and power added efficiency (PAE). The wide operating bandwidth was achieved by using magnetically coupling Balun for the output matching and T-type matching for the inter-stage matching. The measurement results showed a small signal gain of 20.1 dB, the saturated output power (Psat) and OP1dB are 20.1 dBm and 18.4 dBm, respectively. The peak output power and PAE are improved by the amount of 3.8 dB and 3.4%, respectively, while adopted this composited power amplifier architecture. The chip area is 1.78 (1.95×1.13) mm2.
The second and third chips were fabricated in tsmcTM 90-nm CMOS technology for Ka-band operation. Two amplifiers were realized by using unilateralization technique in common-source topology. The input and output matching design followed the previous work and the inter-stage matching was realizes by magnetic transformer.
The third power amplifier applied a pre-matching design to minimize the chip size and increase the operating bandwidth. These power amplifiers displayed the gains of 17.43 dB and 14.5dB, respectively. The saturated output powers were measured to 14.73 dBm and 18.4 dBm. The OP1dB were 10.7dBm and 14.5 dBm, respectively. The chip areas are 0.73 (1.41×0.405) mm2 and 0.67 (1.01×0.67) mm2.
The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2.
The last power amplifier also was fabricated in WINTM 0.25-µm GaN technology. A Doherty power amplifier (DPA) adopted a T-type network for the output matching to reduce the chip size and a Lange-coupler for the input matching. The DPA achieved a peak gain of 11.8 dB, a saturation output power of 35.9 dBm, a PAE at 6-dB power back-off of 39.9% and a peak PAE 41.5%. The chip area is 3.03 (1.73×1.75) mm2.

摘要 I
Abstract III
誌謝 V
目錄 VII
圖目錄 IX
表目錄 XIII
第一章 緒論 1
1- 研究動機 1
1-2 研究成果 1
1-3 章節簡介 2
第二章 應用磁耦合變壓器暨中性化技術寬頻功率放大器設計 3
2-1 研究現況 3
2-2 磁耦合變壓器簡介 3
2-3 單向化電路與中和化電路 6
2-3-1 電路簡介 7
2-3-2 增益與穩定度之改善 10
2-4 應用於Ka頻帶之差動中性化寬頻功率放大器 13
2-4-1 應用於Ka頻帶之差動中性化寬頻功率放大器設計 13
2-4-2 電路模擬與量測結果 25
2-4-3 結果比較與討論 34
2-5 應用於Ka 頻帶之中性化暨預匹配寬頻功率放大器 36
2-5-1 應用於Ka 頻帶之中性化暨預匹配寬頻功率放大器設計 36
2-5-2 電路模擬與量測結果 46
2-5-3結果比較與討論 53
第三章 應用於X頻段之改善增益壓縮暨中性化功率放大器 55
3-1 研究現況 55
3-2 改善電路效率架構 55
3-3 應用於X頻段之改善增益壓縮暨中性化功率放大器 57
3-3-1 應用於X頻段之改善增益壓縮暨中性化功率放大器設計 57
3-3-2 電路模擬與量測結果 65
3-3-3 結果比較與討論 73
第四章 應用X頻段之二元功率結合與多蒂氮化鎵功率放大器 76
4-1 研究現況 76
4-2 多蒂功率放大器簡介 76
4-3 應用X頻帶二元功率結合暨低阻抗匹配之氮化鎵功率放大器 79
4-3-1 應用X頻帶二元功率結合暨低阻抗匹配之氮化鎵功率放大器設計 79
4-3-2 電路模擬與量測結果 85
4-3-3 結果比較與討論 94
4-4 應用於X頻帶之氮化鎵多蒂功率放大器 96
4-4-1 應用於X頻帶之氮化鎵多蒂功率放大器設計 96
4-4-2 電路模擬結果 103
4-4-3 結果比較與討論 108
第五章 結論 109
5-1 結論 109
5-2 未來方向 110
參考文獻 111

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