臺灣博碩士論文加值系統

在本論文中，針對多閘指(multi-finger, MF)與多環狀(multi-ring, MR)金氧半電晶體(MOSFET)在奈米CMOS製程中的佈局效應對於高頻特性如截止頻率(fT)與最大震盪頻率(fMAX)以及射頻雜訊的影響進行深入探討。同時，本研究團隊已發展一套完整萃取流程以精確決定本質元件參數以及寄生電阻、電感與電容(RLC)，此乃關鍵性參數藉以分析、模擬與預測fT, fMAX以及射頻雜訊如雜訊指數(NFmin)與等效雜訊電阻(Rn)。而對於高頻元件參數與特性而言，製程微縮效應則是另一個至關重要的主題。本論文利用台積90奈米與40奈米製程，即TN90GUTMT與N40G，分別設計與研製各種MF與MR nMOSFETs。TN40G製程相較於TN90GUTM製程，其元件佈局規則參數與物理尺寸皆大幅微縮，如閘指長度(Lg)、多晶矽閘指厚度(Tpoly)、接觸金屬厚度(TCO)以及金屬厚度(TM1)微縮52~60%、閘極氧化層厚度(Tox)微縮84%、閘極與接觸窗距離(LPO-CO)微縮42~43%，此一製程微縮效應將會對於本質元件參數、寄生RLC以及更重要的高頻特性產生複雜的影響。基本上，隨著Lg、Tpoly、TCO、TM1以及佈局尺寸的縮減，其缺點為增加閘極電阻(Rg)、接觸窗金屬插柱(contact plug)電阻以及金屬連線所產生源極電阻與電感(RS and LS,int)等，上述寄生效應之增加會導致轉導(gm)、fT以及fMAX降低，尤其甚者會同時惡化其射頻雜訊。然而另一方面，Lg、Tpoly、TCO與TM1微縮卻可能有助於抑制本質寄生電容，如閘指側壁與閘指尾端的邊緣雜散電容(Cof與Cf(poly-end))，得以有效降低閘極電容(Cgg)。實驗數據顯示， Lg微縮幅度大於Tox(或Tox(inv))，依據此製程微縮比例原則得以提升gm以及減少Cgg，對於相同多閘指佈局之元件，受惠於此製程技術微縮比例原則，自TN90GUTM進展到TN40G時其fT得以顯著提升高達60~110%。然而，提高fT並無法保證改善fMAX，乃因閘極電阻Rg大幅增加而超越fT上升所帶來的優點，因此fMAX無法同步提升，甚至可能會降低。可見製程技術微縮與元件佈局效應相關的寄生RLC參數間複雜的消長關係，對於高頻元件設計、寄生RLC萃取與等效電路建模而言乃成為一個有價值且富挑戰性的研究議題。
本論文主要創新成果之一為建立一新式源極與汲極寄生電阻萃取方法，稱為矩陣法(matrix method)，應用於各種MF與MR元件得以準確計算其去寄生效應(deembedding)之前的源極與汲極寄生電阻(RS, RD)。此矩陣法所得RS與RD乃是萃取奈米元件中等效載子遷移率(eff)所需之關鍵性參數，並且藉以驗證其準確性。此矩陣法已應用於TN90GUTM以及TN40G製程所得MF與MR nMOSFET，得以準確計算每一根通道(OD)實際通過的電流以及每一根源極端的電壓值，無須假設電流平均分配於每一根通道與人為虛擬之等電位源極，因此自然解決先前傳輸線模型(TML model)所需假設產生之問題。上述假設在MF元件中有較大閘指數(NF)情況下，往往導致高估其RS，進而誤導eff萃取，造成eff偏高甚至異常躍升之現象。此問題在TN40G相較於TN90GUTM尤其嚴重，可歸因於製程微縮而大幅降低的TM1~M3與TCo所造成之金屬片電阻與接觸窗電阻(RCo)大幅增加。再者，針對MF與MR元件應用於高頻與低雜訊電路設計，如何準確萃取其閘極電阻Rg乃成為一挑戰性且存在諸多爭議之研究題材。其中又分為低頻時的理想Rg以及高頻時的真實Rg，兩者有明顯差異，且隨著MF元件閘指數NF增加而愈益嚴重；而主要的高頻效能參數如fMAX以及雜訊參數Rn與 NFmin乃是決定於與頻率相關之真實Rg。MR元件乃一新式元件佈局結構，相較於MF元件能夠抑制STI橫向壓縮應力(⊥)，應用於nMOSFET中得以增加電子的eff，最終目的為提升gm以及fT。然而MR元件佈局出現一些潛在缺點，例如Rg、Cof與Cf(poly-end)等本質寄生成份增加，反而導致fT、fMAX與NFmin等參數之劣化。因此，如何設計新式MR元件以同時降低Rg、Cof與Cf(poly-end)乃成為未來亟需深入研究之題材。此外，元件本質寄生電感Lg,int、Ld,int與Ls,int乃是影響高頻特性與效能的關鍵要素，且具有複雜之佈局相關性，對於建立真實本質MOSFET模型(actual intrinsic MOSFET model)為必要的寄生效應參數，尤其是應用於極高頻如毫米波電路模擬與設計所不可或缺。
最後，藉由結合真實本質MOSFET模型與本實驗室首創且已驗證完成的損耗基板模型(lossy substrate model)可以建立一完整等效電路，用以模擬未經去寄生效應之高頻特性與射頻雜訊，亦即包括探針墊(GSG pads)與傳輸線(interconnection lines)等產生之雜散寄生效應。然而，自TN90GUTM進展至TN40G時，由於堆疊金屬層與金屬間介電質厚度大幅變薄，導致GSG pads至基板以及連接pads到核心元件之傳輸線所產生的寄生電容巨幅增加，此類外部寄生電容所占的比例遠超過本質元件與本質寄生電容(Cgg,int, Cof,, and Cf(poly-end))。因此，針對TN40G中各式MF元件，其高頻量測數據無法顯示不同MF元件佈局產生之明顯差異，對於去寄生效應造成解析度不足的問題。其去寄生效應之後的反常現象，包括本質Y-參數出現異常的頻率相關性以及正負號反轉等特異結果。上述製程技術微縮產生之問題，對於去寄生效應之準確性與可靠度帶來挑戰，亦即未來亟需研發創新測試結構與方法以有效降低外部寄生電容。最終，損耗基板去寄生效應方法可應用於TN90GUTM與TN40G製程所得MF與MR元件以達到精確萃取其本質高頻雜訊。此方法可以解決傳統習用之雜訊相關矩陣方法(noise correlation matrix method)所產生之問題，並且進一步應用於高頻元件佈局優化以促進利用奈米CMOS製程進行低雜訊之高頻元件與電路設計。

In this thesis, an extensive investigation has been carried out on the layout dependent effects in multi-finger (MF) and multi-ring (MR) nMOSFETs, and the impact on high frequency performance like most importantly unit gain cut-off frequency fT and maximum oscillation frequency fMAX, as well as RF noise in nanoscale CMOS technologies. A comprehensive extraction flow has been developed for accurate determination of the intrinsic device parameters as well as intrinsic parasitic resistances, inductances, and capacitances (RLC), which are key parameters governing fT and fMAX, and RF noise like NFmin and Rn. The impact of technology scaling on high frequency device parameters and performance appears as another critically important topic. In this thesis, 90nm and 40nm CMOS technologies from TSMC, namely TN90GUTM and TN40G have been adopted for MF and MR nMOSFETs design and fabrication. The aggressive scaling of layout rule and physical dimensions like poly gate length (Lg), poly gate thickness (TPO), contact plug thickness (TCO), and metal thickness (TM1) by around 52~60%, gate oxide thickness (Tox) by around 84%, and PO-to-CO space (LPO-CO) by 42~43% from TN90GUTM to TN40G will lead to complicated influence on the intrinsic device parameters, intrinsic parasitic RLC, and more importantly high frequency performance. Basically, the shrinkage of Lg, TPO, TCO, TM1, and layout dimensions can lead to the increase of gate resistance (Rg), contact resistance, and source parasitic resistance as well as inductance (RS and LS,int) in MF devices with extended source line, all of which may cause the penalties such as degradation of transconductance (gm), fT and fMAX, and even worse the increase of RF noise (Rn and NFmin). On the other hand, the scaling of Lg, TPO, TCO, and TM1 can help suppress the intrinsic parasitic capacitances like gate sidewall and finger-end fringing capacitances (Cof and Cf(poly-end)) and achieve smaller gate capacitance (Cgg). The experimental results indicate that more aggressive scaling in Lg than Tox (or Tox(inv)) can achieve higher gm and smaller Cgg, and thus significant boost of fT by around 60 ~110% in MF nMOSFETs attributed to technology scaling from TN90GUTM to TN40G. However, the higher fT cannot guarantee the higher fMAX because that the dramatic increase of Rg may overwhelm the advantage of fT and result in similar or even lower fMAX. It means that the complicated trade-off between the parasitic RLC associated with technology scaling and layout dependent effects becomes a valuable and challenging topic for high frequency devices design, parasitic RLC extraction, and equivalent circuit modeling.
In this thesis, a new method, namely matrix method for accurate extraction of extrinsic source and drain parasitic resistances, RS and RD in MF and MR MOSFETs, has been developed and proven with sufficient accuracy for effective mobility eff extraction in MF and MR nMOSFETs associated with TN90GUTM and TN40G technologies. This matrix method can accurately determine the current through every active channel (OD) finger and voltage at each source finger terminal, and thus solve the problem from previous assumption of uniform current distribution and equal source terminal voltage at every finger. The mentioned assumption may lead to sever over-estimation of extrinsic RS and an abnormal jump of eff extracted from MF nMOSFETs in case of larger finger number (NF). This problem becomes particularly worse in TN40G technology than TN90GUTM, due to the aggressive scaling of TM1~M3 and TCO, as well as significant increase of the metal sheet resistance and contact resistance (RCO). Furthermore, how to determine the physical Rg and real Rg through high frequencies responsible for fMAX, Rn, and NFmin becomes a challenging topic of controversy, particularly for MF and MR devices with extremely narrow finger width (WF) in case of very large NF. MR devices proposed as a solution for higher eff attributed to suppression of STI compressive transverse stress ⊥. However, some potential problems like the increase of Rg, Cof, and Cf(poly-end) may be detrimental to fT, fMAX, and RF noise (Rn, and NFmin). Some innovative MR layouts for simultaneous reduction of Rg, Cof, and Cf(poly-end) emerge as another topic worthy of further study. In addition, the intrinsic parasitic inductances like Lg,int, Ld,int, and Ls,int appear as critical elements with sophisticated layout dependence and influence on high frequency parameters, which are dispensable for actual intrinsic MOSFET models for high frequency simulation aimed at mm-wave circuits design.
Finally, the actual intrinsic MOSFET models can be integrated with our proprietary lossy substrate model to build up a full equivalent circuit model for both high frequency and RF noise simulation prior to deembedding. However, the aggressive thickness reduction of the stacked metal layers and inter-metal dielectric in technology scaling from TN90GUTM to TN40G causes dramatic increase of parasitic capacitances associated with the GSG pads and interconnection lines from the pads to the core devices. This kind of extrinsic parasitic capacitances may overwhelm the intrinsic channel and frigning capacitances (Cgg,int, Cof,, and Cf(poly-end)), which may lead to very minor difference between various MF layouts and difficulty in open deembedding. As a result, the intrinsic Y-parameters reveal anomalous frequency dependence and reverse of positive/negative sign. It emerges as a new challenge to precise deembedding and suggests more extensive research effort in the future for effective reduction of the extrinsic parasitic capacitances. To the end, our proprietary lossy substrate deembedding method can be applied for accurate extraction and simulation of intrinsic RF noise in MF and MR devices associated with TN90GUTM and TN40G technologies. This way can eliminate the problems of conventional noise correlation matrix method and facilitate device layouts optimization for high frequency and low noise design in nanoscale CMOS technologies.

Chinese Abstract i
Abstract iv
致謝 viii
Contents ix
Figure Captions xiii
Table Captions xxxvii
Chapter 1 Introduction 1
1.1 Research Motivation 1
1.2 Overview 2
Chapter 2 Fundamental Theory and Measurement Techniques 5
2.1 Scattering Matrix and Parameters 5
2.1.1 Two-Port Network Analyzer Measurement Techniques 5
2.1.2 Two Steps De-embedding Method 6
2.2 Thermal Noise Theory and Measurement Method 8
2.2.1 Thermal Noise Sources 8
2.2.2 Two-port Noise Theory 9
2.2.3 High Frequency Noise Measurement System and Method 10
Chapter 3 DC Characteristics and Layout dependent effects of Multi-finger (MF) and Multi-Ring (MR) nMOSFETs – Comparison of TN90GUTM and TN40G 13
3.1 MF and MR nMOSFETs Layouts in TN90GUTM and TN40G 13
3.2 The Layout Dependent effect on Threshold Voltage (VT) and Induced Barrier Lowering (DIBL) 16
3.2.1 Layout Dependent Effects in Threshold Voltage (VT) and Mechanisms Analysis 16
3.2.2 Layout Dependent and Technology Scaling Effects in Drain Induced Barrier Lowering (DIBL) and Mechanisms Analysis 23
3.3 Source Resistance Extraction Methods and Verification 25
3.3.1 Transmission Line Model for RS Extraction in 4T MF nMOSFETs 25
3.3.2 Matrix Method for Accurate RS Extraction in 4T MF MOSFETs 30
3.3.3 Matrix Method for Accurate RS Extraction in 3T MR nMOSFETs 34
3.4 Layout Dependant Fringing Capacitance Analysis and Effective Mobility Extraction Method 39
3.4.1 3-D Fringing Capacitance Simulation and Analysis by Raphael 39
3.4.2 I-V Characteristics and Effective Mobility Extraction for MF and MR nMOS 50
3.5 A Comparison of DC Characteristics between MF and MR nMOSFETs in TN90GUTM and TN40G 55
Chapter 4 High Frequency Characteristics and Layout Dependent Effects in 3T MF and MR nMOS 63
4.1 High Frequency Performance Parameters Extraction and Analysis with Layout Dependent Effect 63
4.1.1 The Cut-Off Frequency fT Analysis 64
4.1.2 The Maximum Oscillation Frequency fMAX Analysis 73
4.2 New De-embedding Method based on MF Field nMOS 78
4.2.1 MF Field nMOSFETs Layouts in TN40G 78
4.2.2 The Effective Mobility Extraction for MF nMOSFETs and New De-embedding method with MF Field nMOS 81
4.2.3 A Comparison of High Frequency Performance between OpenM1 and Field De-embedding 89
Chapter 5 Noise Analysis and Simulation in 3T MF and MR nMOSFETs Analysis Based on Small Signal Model 91
5.1 Lossy Substrate RLC Network Model 91
5.2 Small Signal Equivalent circuits in 3T MF and MR nMOSFETs for High Frequency Simulation 105
5.2.1 Actual Intrinsic MOSFET Model for Accurate Simulation of High Frequency and Layout Dependence in 3T MF and MR nMOSFETs under Cold Region 105
5.2.2 High Frequency Simulation for 3T MF and MR nMOSFETs after De-embedding -Actual Intrinsic MOSFET Model 130
5.2.3 High Frequency Simulation for 3T MF and MR nMOSFETs before De-embedding – Full Equivalent Circuit Models 143
5.3 High Frequency Noise Analysis and Simulation for 3T MF and MR nMOSFETs in TN90GUTM and TN40G 150
5.3.1 High Frequency Noise Parameters in 3T MF and MR nMOSFETs – Layout Dependent Effects 150
5.3.2 RF Noise Parameter in 3T MF and MR nMOS– Analysis by full equivalent circuit simulation 156
5.3.3 A Comparison of Intrinsic Noise Parameters Extracted by Noise Correlation Matrix and Lossy Substrate Deembedding Method 170
5.3.4 High Frequency Noise Simulation by Equivalent Circuit Models Before and After Deembedding 178
5.3.5 A comparison of High Frequency Noise Simulation between ideal devices with and without Rg 184
Chapter 6 Conclusion and Future Work 196
6.1 Conclusion 196
6.2 Future Work 199
Reference 201

[1] R.M. Fox, "Comments on Circuit Models for MOSFET Thermal Noise," IEEE J. Solid-State Circuits, vol. 28, no. 2, pp. 184-185, Feb. 1993.
[2] C.H. Chen and M.J. Deen, "High Frequency Noise of MOSFETs I Modeling," Solid-State Electronics, vol. 42, no. 11, pp. 2069-2081, 1998.
[3] S.V. Kishore, G. Chang, G. Asmanis, C. Hull, and F. Stubbe, "Substrate-Induced High-Frequency Noise in Deep Sub-Micron MOSFETs for RF Applications," in Proc. IEEE Custom Integrated Circuits Conf., CA, 1999, pp. 365-368.
[4] M.V. Dunga, X. Xi, J. He, W. Liu, K.M. Cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, C. Hu, "BSIM460 Manual," Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA, 2006.
[5] N. Shigyo and R.L.M. Dang, "Analysis of Inverse Narrow-Channel Effect Based on a Three-Dimensional Simulation," in VLSI Symp. Tech. Dig., 1982, pp. 54-55.
[6] C.-C. Wang, W. Zhao, F. Liu, M. Chen, and Y. Cao, "Modeling of Layout-Dependent Stress Effect in CMOS Design," in Proc. IEEE/ACM ICCAD, 2009, pp. 513-520.
[7] M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, "Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 440-443, March 2004.
[8] Y.-M. Sheu, S.-J. Yang, C.-C. Wang, C.-S. Chang, L.-P. Huang, T.-Y. Huang, M.-J. Chen, and Carlos H. Diaz, "Modeling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30-38, Jan. 2005.
[9] D. Pramanik, "Impact of Layout on Variability of Devices for Sub 90nm Technologies," IEEE Electron Devices Society Santa Clara Chapter Meeting, 2006.
[10] P.R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, "Fundamentals of Silicon Material Properties for Successful Exploitation of Strain Engineering in Modern CMOS Manufacturing," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 944-964, May 2006.
[11] Y. Sun, S.E. Thompson, and T. Nishida, "Physics of Strain Effects in Semiconductors and Metal-Oxide-Semiconductor Field-Effect Transistors," J. Appl. Phys., vol. 101, no. 10, pp. 104503-1-104503-22, May 2007.
[12] T.-K. Kang, "Evidence for Silicon Bandgap Narrowing in Uniaxially Strained MOSFETs Subjected to Tensile and Compressive Stress," IEEE Electron Device Lett., vol. 33, no. 6, pp. 770-772, June 2012.
[13] J.-S. Lim, S.E. Thompson, and J.G. Fossum, "Comparison of Threshold-Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs," IEEE Electron Device Lett., vol. 25, no. 11, pp. 731-733, Nov. 2004.
[14] C.-Y. Hsieh, and M.-J. Chen, "Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 844-849, March 2008.
[15] N.E.B. Cowern, P.C. Zalm, P. van der Sluis, D.J. Gravesteijn, and W.B. de Boer, "Diffusion in Strained Si(Ge)," Phys. Rev. Lett., vol. 72, no. 16, pp. 2585-2588, Apr. 1994.
[16] P. Sallagoity, M. Ada-Hanifi, M. Paoli, and M. Haond, "Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1900-1906, Nov. 1996.
[17] L.A. Akers, "The Inverse-Narrow-Width Effect," IEEE Electron Device Lett., vol. 7, no. 7, pp. 419-421, July 1986.
[18] K.-L. Yeh, and J.-C. Guo, "A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs," IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 2838-2846, Sep. 2011.
[19] Jyh-Chyurn Guo, Kuo-Liang Yeh, US patent 8,691,599 B2, July 2011 ~ Nov. 2032.
[20] C.H. Wang, and P.-F. Zhang, "Three-Dimensional DIBL for Shallow-Trench Isolated MOSFET's," IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 139-144, Jan. 1999.
[21] K.-L. Yeh and J.-C Guo, "Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs," IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 109-116, Jan. 2013.
[22] Yi-Jen Lou, "Layout Dependent Parasitic and Device Parameters Extraction Methods for RF CMOS Simulation and Noise Analysis in Nano Si CMOS Technology," Master Thesis, National Chiao-Tung University, 2015.
[23] K.-L. Yeh and J.-C. Guo, "Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs," IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3140-3146, Sep. 2011.
[24] Y. Cheng, M. Chan, K. Hui, M.-C. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P.K. Ko, and C. Hu, "BSIM3v3 Manual," Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA, 1995.
[25] K.-L. Yeh and J.-C. Guo, "The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 3092-3100, Nov. 2010.
[26] C.-Y. Hsieh and M.-J. Chen, "Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed nMOSFETs," IEEE Electron Device Lett., vol. 28, no. 9, pp. 818-820, Sep. 2007.
[27] I. Kwon, M. Je, K. Lee, and H. Shin, "A Simple and Analytical Parameter-Extraction Method of a Microwave MOSFET," IEEE Trans. Microw. Theory Tech., vol. 50, no. 6, pp. 1503-1509, June 2002.
[28] S. Lee, H.K. Yu, C.S. Kim, J.G. Koo, and K.S. Nam, "A Novel Approach to Extracting Small-Signal Model Parameters of Silicon MOSFET's," IEEE Microw. Guided Wave Lett., vol. 7, no. 3, pp. 75-77, March 1997.
[29] M. Kang, I.M. Kang, and H. Shin, "Extraction and Modeling of Physics-Based Gate Resistance Components In RF MOSFETs," Silicon Monolithic Integr. Circuits RF Syst. Dig., pp. 218-221, Jan. 2006.
[30] M. Kang, I.M. Kang, Y.H. Jung, and H. Shin, "Separate Extraction of Gate Resistance Components in RF MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1459-1463, June 2007.
[31] P. Yang, B.D. Epler, and P.K. Chatterjee, "An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation," IEEE J. Solid-State Circuits, vol. SSC-18, pp. 128-138, Feb. 1983.
[32] X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M.J. Deen, P.R. Gray, and C. Hu, "An Effective Gate Resistance Model for CMOS RF and Noise Modeling," in IEDM Tech. Dig., 1998, pp. 961-964.
[33] M. Chan, K. Hui, R. Neff, C. Hu, and P.K. Ko, "A Relaxation Time Approach to Model the Non-Quasi-Static Transient Effects in MOSFET's," in IEDM Tech. Dig., 1994, pp. 169-172.
[34] Y. Cheng and M. Matloubian, "High Frequency Characterization of Gate Resistance in RF MOSFETs," IEEE Electron Device Lett., vol. 22, no. 2, pp. 98-100, Feb. 2001.
[35] Kuan-Hsu Chen, "RF MOSFET Small Signal Equivalent Circuit Model Parameter Extraction for Various Biases and Geometries," Master Thesis, National Chiao-Tung University, 2008.
[36] Kuo-Liang Yeh, " Nano Si CMOS Devices Modeling and Parameters Extraction Methods for Layout Dependent Effects and Strain Engineering in High Frequency Simulation and Noise Analysis," PhD Thesis, NCTU, 2017.
[37] T. Manku, "Microwave CMOS-Device Physics and Design," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 277-285, March 1999.
[38] W.H. Ku, "Unilateral Gain and Stability Criterion of Active Two-Ports in Terms of Scattering Parameters," Proc. IEEE, vol. 54, no. 11, pp. 1617-1618, Nov. 1966.
[39] A. van der Ziel, "Thermal Noise in Field-Effect Transistors," Proc. IRE, vol. 50, no. 8, pp. 1808-1812, Aug. 1962.
[40] Jyh-Chyurn Guo and Chih-Ting Yeh, "A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs," IEEE Transactions on Electron Devices, vol.56, no.8, pp.1598-1607, 2009.
[41] L. F. Tiemeijer , R. J. Havens , R. de Kort , A. J. Scholten , R. van Langevelde , D. B. M. Klaassen , G. T. Sasse , Y. Bouttement , C. Petot , S. Bardy , D. Gloria , P. Scheer , S. Boret , B. Van Haaren , C. Clement , J.-F. Larchanche , I.-S. Lim , A. Duvallet and A. Zlotnicka "Record RF performance of standard 90 nm CMOS technology", in IEDM Tech. Digest, 2004, pp.441-444
[42] I. Post , M. Akbar , G. Curello , S. Gannavaram , W. Hafez , U. Jalan , K. Komeyii , J. Lin , N. Lindert , J. Park , J. Rizk , G. Sacks , C. Tsai , D. Yeh , P. Bai and C.-H. Jan "A 65 nm CMOS SOC technology featuring strained silicon transistors for RF applications," in IEDM Tech. Digest, 2006, pp.1013-1015.
[43] H. Li , B. Jagannathan , J. Wang , T.-C. Su , S. Sweeney , J. J. Pekarik , Y. Shi , D. Greenberg , Z. Jing , R. Groves , L. Wagner and S. Csutak "Technology scaling and device design for 350 GHz RF performance in 45 nm bulk CMOS process," in VLSI Tech. Symp. Proceedings, 2007, pp.56-57.
[44] P. VanDerVoorn , M. Agostinelli , S.-J. Choi , G. Curello , H. Deshpande , M. A. El-Tanani , W. Hafez , U. Jalan , L. Janbay , M. Kang , K.-J. Koh , K. Komeyli , H. Lakdawala , J. Lin , N. Lindert , S. Mudanai , J. Park , K. Phoa , A. Rahman , J. Rizk , L. Rockford , G. Sacks , K. Soumyanath , H. Tashiro , S. Taylor , C. Tsai , H. Xu , J. Xu , L. Yang , I. Young , J.-Y. Yeh , J. Yip , P. Bai and C.-H Jan "A 32 nm low power RF CMOS SOC technology featuring high-k/metal gate," in Symp. VLSI Tech. Digest, 2010, pp.137-138.
[45] B. Heydari , M. Bohsali , E. Adadi and A. M. Niknejad "Millimeter-wave devices and circuit blocks up to 10 GHz in 90 nm CMOS", IEEE J. Solid State Circuits, vol. 42, no. 12, pp.2893 -2903, 2007
[46] Jyh-Chyurn Guo and Yi-Min Lin, "A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling," IEEE Transactions on Electron Devices, vol. 53, pp. 339-347, 2006.
[47] Yi-Hsiu Tsai, "The Lossy Substrate Model for RF MOSFET High Frequency Noise Simulation under Various Pad Structures," Master Thesis, NCTU, 2007.
[48] Yen-Ying Lin, " Parameters Extraction and Analytical Models for Layout Dependent Effects in DC and HF Characteristics of Nanoscale CMOS Devices," Master Thesis, NCTU, 2015.
[49] Jyun-Rong Ou, " New Methods for intrinsic Parasitic RLC Extraction and Small signal Equivalent Circuit Models for High Frequency and RF Noise Simulation in 3T and 4T Nanoscale Multi-finger MOSFETs," Master Thesis, NCTU, 2018.
[50] Jyh-Chyurn Guo and Yi-Hsiu Tsai, "A Broadband and Scalable Lossy Substrate Model for RF Noise Simulation and Analysis in Nanoscale MOSFETs With Various Pad Structures," IEEE Transactions on Microwave Theory and Techniques, vol. 57, pp. 271-281, 2009.
[51] D. Lovelace, J. Costa, N. Camilleri, "Extracting small-signal model parameters of silicon MOSFET transistors", IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, pp. 865-868, 1994.
[52] Y. Cheng, M. J. Deen, C.-H. Chen, "MOSFET modeling for RF IC design", IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1286-1303, Jul. 2005.
[53] A. Bracale, D. Pasquet, J. L. Gautier, V. Ferlet, N. Fel, J. L. Pelloie, "Small signal parameters extraction for silicon MOS transistors", Eur. Microw. Conf., pp. 1-4, 2000-Oct.
[54] R. Torres-Torres, R. Murphy-Arteaga, S. Decoutere, "MOSFET bias dependent series resistance extraction from RF measurements", Electron. Lett., vol. 39, pp. 1476-1478, Oct. 2003.
[55] Yi-Min Lin, "Lossy Substrate De-embedding Method for RF MOSFET Intrinsic Noise Extraction," Master Thesis, NCTU, 2006.
[56] Y. Cheng, M. Matloubian, "On the high-frequency characteristics of substrate resistance in RF MOSFETs," IEEE Electron Device Lett., vol. 21, no. 12, pp. 604-606, Dec. 2000.
[57] Jonghwan Lee, Gijs Bosman, Keith R. Green, D. Ladwig, "Noise Model of Gate-Leakage Current in Ultrathin Oxide MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 12, dec. 2003.
[58] H. Hillbrand and P. Russer, "An efficient method for computer aided noise analysis of linear amplifier networks," IEEE Transactions on Circuits and Systems, vol. 23, pp. 235-238, 1976.
[59] H. A. Haus and R. B. Adler, Circuit theory of linear noisy networks: The MIT Press, 1959.
[60] D. D. Lu, "Compact models for future generation CMOS," Ph.D. Dissertation, U.C. Berkely, 2011.
[61] S. Asgaran, M. J. Deen, C. H. Chen, G. A. Rezvani, Y. Kamali, Y. Kiyota, " Analytical determination of MOSFET's high-frequency noise parameters from 50 measurements and its application in RFIC design ", IEEE J. Solid-State Circuits, vol. 42, pp. 1034-1043, May 2007.
[62] Jyh-Chyurn Guo and Yi-Min Lin, "A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1684-1688, 2008.
[63] J.-S. Goo, S. Donati, C.-H. Choi, Z. Yu, T. H. Lee, and R. W. Dutton, "Impact of substrate resistance on drain current noise in MOSFETs," in Simulation of Semiconductor Processes and Devices 2001, ed: Springer, 2001, pp. 182-185.