臺灣博碩士論文加值系統

在無線通訊領域研究與發展上，渦輪碼一直佔有重要的地位，因其使用一疊代解碼演算法使得它的解碼能力趨近於仙農極限。現代無線通訊協定上，資料產出量是其中一個嚴苛的要求，研究者於是發展出平行解碼及高基數架構來滿足此要求，然而兩者皆會縮短交錯器可交錯之距離進而影響到解碼能力。因此本論文提出一個新型雙相式解碼架構應用於兩顆軟資訊解碼器上，能在解碼能力與資料產出量中間取得一平衡，並且透過改善交錯器硬體架構和操作兩顆軟資訊解碼器使用量來分別減少17%晶片面積及有效地降低功率消耗。
我們根據不同解碼時相時間來決定軟資訊解碼器的使用量，在循序解碼時相使用兩顆軟資訊解碼器來做平行解碼，但是在交錯時相只用一顆軟資訊解碼器來解碼以避免解碼效能的降低，實驗結果顯示解碼效能與平行解碼相比能提升0.2dB。我們將所提出的雙相式平行渦輪解碼器驗證在Xilinx Virtex-5 FPGA上，仿真結果顯示具有解碼能力且當工作頻率為100 MHz及消耗功率在255 mW 的時候能提供7.5Mb/s資料產出量。另外我們也採用TSMC 0.18 μm 1P6M CMOS製程來完成晶片合成與佈局，量測的晶片大小為3.03mm2 含有130285邏輯閘數量。

Turbo codes use an iterative algorithm that allows the BER performance to achieve the Shannon limit to carry out decoding. Relative literatures and developments have been researched over decades. One of the requirements of communication standard is throughput which can be satisfied by using parallel or high radix architecture. However, both methods would cause the degradation of the BER performance because they shorten the interleaver length. Hence, we propose a dual phase decoding architecture for two SISO decoders based on different decoding phase. Compared with traditional parallel turbo decoder, the BER performance can improve about 0.2 dB. Experimental results show that our chip can decrease 17% chip area and can reduce power consumption effectively. Also emulation of the Xilinx Virtex-5 FPGA board shows that our turbo decoder can achieve 7.5 Mb/s throughput while operating at 100 MHz, and only consumes 255 mW. We also use TSMC 0.18 μm 1P6M CMOS technology to synthesis and layout our turbo decoder, the decoder chip size including pads is 3.03 mm2 with 130k gate counts.

Chinese Abstract... i
English Abstract... ii
Acknowledgement.... iii
Contents........... iv
Table Contents..... vi
Figure Contents.... vii
1 Introduction.....1
1.1 Background..... 1
1.2 Motivations.. 2
1.3 Thesis Outline........ 3
2 Turbo Codes ......4
2.1 Turbo Encoder ........ 5
2.2 Interleavers.......... 6
2.2.1 Block Interleavers......... 6
2.2.2 Random Interleavers........ 7
2.3 Iterative Algorithms.. 8
2.3.1 The MAP Algorithm..... 9
2.3.2 The Max-Log-MAP Algorithm....... 14
2.3.3 The Log-MAP Algorithm........... 16
3 Design and Architecture of the Dual Phase Parallel Turbo Decoder...... 18
3.1 Traditional Sliding Window Technique...... 18
3.2 Parallel Sliding Window Technique......... 19
3.3 Dual Phase Decoding Sliding Window Technique....... 20
3.4 ASIC Architecture of the Dual Phase Parallel Turbo Decoder.. 23
3.4.1 Received Data RAM.......... 24
3.4.2 Interleaver ROM............ 25
3.4.3 Extrinsic Information RAM.. 27
3.4.4 VLSI Architectures of the SISO Decoder........ 30
3.4.4.1 Branch Metrics Unit.. 31
3.4.4.2 State Metrics Unit – Alpha, Beta, and Beta_int........... 31
3.4.4.2.1 ACSO Circuit. 32
3.4.4.2.2 Normalization Circuit....... 33
3.4.4.3 State Metrics Memory.......... 34
3.4.4.4 LLR Unit............ 34
3.4.4.5 Extrinsic Information Unit.... 35
Chapter 4 Verifications of the Dual Phase Parallel Turbo Decoder.. 36
4.1 System Specifications.... 36
4.2 RTL Simulations.......... 38
4.3 Emulations of the FPGA Board....... 40
4.3.1 Power Estimation.... 42
4.4 Chip Synthesis and Layout ..........43
4.5 Implementation Results and Comparisons...... 45
4.5.1 BER Performance..... 46
4.5.2 Power Consumption.......... 46
4.5.3 Chip Size......... 47
4.5.4 Latency and Throughput...... 47
4.5.5 Table Comparison.. 47
Chapter 5 Conclusions....... 48
References......... 49
Appendix：Unpublished Paper. 51

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