臺灣博碩士論文加值系統

由於鎖相迴路中使用的每一個元件均會貢獻雜訊而影響其抖動量。另外在晶片系統中，供應電源與基板也會注入雜訊至鎖相迴路，其惡化抖動量(jitter)甚鉅。因此本論提出改善方式進而降低抖動量,包括在電荷充放電路(Charge pump)中增設自我調整機制以消除輸出電流之不對稱，此舉亦可加大電壓控制震盪器(Voltage-controlled oscillator)的控制電壓範圍。理論上三階迴路濾波器(Loop filter)要比二階抗雜訊能力來的好，不過也因其迴路頻寬較小而致使系統鎖定時間的延長。同時本電路提出一切換機制並適當地切換此兩種形式迴路濾波器以獲取彼此的優點；為因應其切換機制必須把整個迴路濾波器整合至單一晶片上，故晶片面積的節省以及雜訊之隔離皆是電路設計上的課題；在此以電容放大電路避免消耗過多晶片面積。額外加入的低壓降線性穩壓器(Low dropout voltage regulator)則是有效阻絕雜訊回灌並提供一穩定的電壓予迴路濾波器。在整個系統中占重要地位的電壓控制震盪器是一極敏感元件，我們利用粗調與細調的機制供給電流予延遲單元，其可調整壓控震盪器之增益以降低外界雜訊干擾。

Each device has been employed in PLL would contribute the unavoidable noise to degrade the jitter performance. In addition, the power/ground and substrate noise injected to PLL which integrated in a chip also aggravates jitter heavily. This thesis proposed some improvements for the essential issue of low jitter. We consequently improve the circuit architecture of each device and described it as following. One of that is to add self-adjusted mechanism into a charge pump to eliminate whose output current mismatch; furthermore, the mechanism is capable to extend the control voltage range of Voltage-controlled oscillator (VCO). On the other hand, because of the third-order loop filter with smaller bandwidth, it performs better noise suppression ability than the second-order loop filter does; nonetheless, the third-order presents longer acquisition time. In order to obtain the advantages of both two types of loop filters, a proposed switching mechanism has been utilized to select them appropriately. To accommodate the switching mechanism, we design the loop filter for monolithic integration; as a result, both saving silicon area and isolating noise are main concerns while designing it. By using capacitor multiplier to avoid large amount silicon occupation and utilizing an additive low dropout voltage regulator (LDO), the noise injection can be isolated and a stable supply voltage is also provided for the loop filter. The VCO plays an important role in the whole system whereas it is an extremely sensitive device. Therefore, coarse and fine tuning mechanisms are employed in current-starved elements for delay cells that can lead to the VCO gain (KVCO) tunable and then mitigate the disturbance of external noise.

中文摘要 i
Abstract ii
誌謝 iv
Table of contents v
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of Thesis 2
Chapter 2 The Principles of Phase-Locked Loop 3
2.1 PLL Background Theory 3
2.2 PLL Building Block 5
2.2.1 Phase Frequency Detector (PFD) 5
2.2.2 Charge Pump (CP) 8
2.2.3 Voltage-Controlled Oscillator (VCO) 11
2.2.4 Frequency Divider (FD) 12
2.2.5 PLL Close Loop Analysis 13
2.2.6 Third Order PLL 14
2.2.7 Fourth Order PLL 18
2.3 PLL Noise Source Analysis 20
2.4 Jitter in PLL 22
2.5 System Simulation 23
Chapter 3 Design and Implementation of Low Jitter PLL 25
3.1 Introduction 25
3.2 Operation of the Proposed PLL 26
3.2.1 The Lock Detector (LD) 27
3.2.2 The Switching Mechanism 28
3.3 Circuit Realization 32
3.3.1 Phase Frequency Detector 32
3.3.2 Charge Pump with Mismatch Elimination 34
3.3.3 Third Order Loop Filter with Capacitor Multiplication 39
3.3.4 Low Dropout Voltage Regulator 43
3.3.5 Voltage-controlled oscillator 48
3.3.6 Frequency Divider 52
3.4 Simulation Results 53
3.5 Measurement results 59
3.5.1 Measurement Setup 59
3.5.2 Measurement Results 60
Chapter 4 Conclusions 65
References 66
Appendix A 70

[1] F. M. Gardner, Phaselock Techniques, 2nd Edition, New York: Wiley, 1979.
[2] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
[3] C. W. Lai, “Design of low-jitter adaptive bandwidth PLL based on self-biased techniques,” Master thesis, NCU, Department of Electrical Engineering, June 2005.
[4] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331-343, March 1996.
[5] P. Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, no. 5, pp.744-748, May 1996.
[6] H. H. Chang and J. C. Wu, “A 723-MHz 17.2-mW CMOS programmable counter,” IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1572-1575, Oct. 1998.
[7] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor application note 1001, May 1996.
[8] D. Banerjee, PLL Performance, Simulation, and Design, 3rd Edition, National Semiconductor, 2003.
[9] J. M. Hsu, “Design and application of CMOS PLL/DLL,” Master thesis, NTU, Department of Electrical Engineering, June 1999.
[10] P. Heydari, “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Transactions on Circuits and Systems Ⅰ, vol. 51, no. 12, pp. 2404-2416, Dec. 2004.
[11] A. Hajimiri, “Noise in phase-locked loops,” in IEEE Southwest Symposium on Mixed-Signal Design 2001, 25-27 Feb. 2001, pp. 1-6.
[12] C. H. Lee, J. Cornish, K. McClellan, and J. C. Jr., “Design of low jitter PLL for clock generator with supply noise insensitive VCO,” in IEEE Int. Symposium on Circuits and Systems, May 1998, pp. 233-236.
[13] F. Herzel, B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Transactions on Circuits and Systems Ⅱ, vol. 46, no. 1, pp. 56-62, Jan. 1999.
[14] S. K. Kao, “Design of a PLL with fast-lock and low jitter,” Master thesis, NTU, Department of Electrical Engineering, June 2001.
[15] P. J. Lin, “Design of digital control wide range frequency synthesizer,” Master thesis, NTUT, Institute of Computer and Communication, June 2006.
[16] A. Sedra and K. C. Smith, “A second-generation current conveyor and its applications,” IEEE Transactions on Circuit Theory, pp.132-134, Feb. 1970.
[17] M. G. Johnson and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. 23, no.5, pp.1218-1223, Oct. 1988.
[18] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp.1599-1607, Nov. 1992.
[19] T. C. Lee and B. Razavi, “A stabilization technique for phase-locked frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp.888-894, June 2003.
[20] P. Larsson, “An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5Gb/s optical communication,” in IEEE Int. Solid-State Circuits Conf. 2001 Dig. Tech. Papers, Feb. 2001, pp.74-75.
[21] C. C. Chen, S. C. Lee, and S. I. Liu, “A capacitor multiplication technique using a second-generation current conveyor,” in VLSI CAD 2006.
[22] C. H. Lee, J. Cornish, K. McClellan, and J. C. Jr., “Design of low jitter PLL for clock generator with supply noise insensitive VCO,” in IEEE Int. Symposium on Circuits and Systems, May 1998, pp. 233-236.
[23] T. Sun, C. Hui, and Y. Wang, “A VCO with high supply noise rejection and its application to PLL frequency synthesizer,” in IEEE Int. Symposium on Communications and Information Technology, vol. 2, Oct. 2005, pp. 993-996.
[24] C. H. Lee, K. McClellan, and J. C. Jr., “A supply-noise-insensitive CMOS PLL with a voltage regulator using dc-dc capacitive converter,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1453-1463, Oct. 2001.
[25] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998.
[26] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp.1723- 1732, Nov. 1996.
[27] W. S. T. Tan and H. C. Luong, “A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,” IEEE Transactions on Circuits and SystemsⅡ, vol. 48, no. 2, pp.216-221, Feb. 2001.
[28] S. B. Anand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 432-439, March 2001.
[29] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 761-767, May 2001.
[30] K. H. Cheng, C. W. Lai, and Y. L. Lo, “A CMOS VCO for 1V, 1GHz PLL applications,” in IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 2004, 4-5 Aug. 2004, pp. 150-153.
[31] T. Wu, K. Mayaram, and U. K. Moon, “An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators,” IEEE J. Solid-State Circuits, vol. 42, no.4, pp. 775-783, April 2007.