臺灣博碩士論文加值系統

本論文首先使用TSMC 0.35µm 2P4M CMOS製程來實現電阻補償技術之能隙參考電路及參考電流，該電路係由多種具高正溫度係數的電阻、二級運算轉導放大器與簡化的啟動電路所組成。本論文所提出之能隙參考電路係利用雙極性電晶體的n-p-n與p-n-p接面的寄生電阻為補償電阻，藉以產生與溫度無關之電壓和電流參考電路。當電源供應電壓為3.3 V時，該電路所量測到的參考電流為735.6奈安培(nA)，且參考電壓為888.1毫伏特(mV)，得到的功率消耗為91.28微瓦特(µW)。此外，量得的電壓溫度係數在溫度0oC ~100oC與30oC ~100oC分別為49 ppm/oC和12.8 ppm/oC，而其電流溫度係數在溫度0oC ~100oC則為119.2 ppm/oC；再者，該帶差參考電路在溫度大於30oC時可以產生穩定的參考電壓，而在溫度小於70oC時可以產生穩定的參考電流。
其次，本論文使用TSMC 0.18µm 1P6M CMOS製程來設計並實現二種調變器晶片，第一種晶片是具有類比式錯誤消除邏輯電路與數位式梳型濾波器的全差動三級(二加一階)串接切換電流式三角積分調變器；而第二種晶片是使用四位元切換電容式快閃類比數位轉換器與增加式資料加權平均器之三階多位元切換電流式三角積分調變器。在該二種晶片之中，本論文提出一個電流式記憶單元，其可利用回授電路來降低輸入阻抗，並可利用共模前饋電路來改善輸出共模位準的差動取樣保持電路，該電路主要用於組成三角積分調變器之離散積分器。
二加一階三角積分調變器是將第一級量化器輸入端接到第二級，此方式不僅降低電路的複雜度，同時容易以切換電流技術來完成。在調變器中，最主要的誤差(e2)是由第二級的一位元量化器所產生，並且可以藉由類比式錯誤消除邏輯電路來消除這個誤差。此晶片量測結果顯示，在電源供應電壓為1.8伏特(V)且取樣頻率為10.24 MHz、超取樣率為128，且頻寬為40 kHz時可以得到訊號雜訊比為67.3 dB、有效位元數為10.9位元(bits)、動態範圍為69 dB以及功率消耗為12.3毫瓦特(mW)，且其晶片面積約為0.20 × 0.21毫米平方(mm2)。
第二種晶片係使用TSMC 0.18µm 1P6M CMOS製程來設計並實現一個三階多位元切換電流式三角積分調變器，其利用四位元切換電容式快閃類比數位轉換器來提高解析度，並使用增加式資料加權平均器將數位類比轉換器(DAC)所產生的誤差移到信號頻寬外，並且做一階的雜訊頻移。晶片量測結果顯示，在電源供應電壓為1.8伏特(V)、取樣頻率為10.24 MHz、超取樣率為256且頻寬為20 kHz時，可以得到訊號雜訊比為60.87 dB、有效位元數為9.82位元(bits)、動態範圍為60 dB以及功率消耗18.82毫瓦特(mW)，且其晶片核心面積為0.45 × 0.67毫米平方(mm2)。

Firstly, this dissertation investigates a resistor-compensation technique for CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. Because of the simplified start-up circuit, the proposed resistor-compensation bandgap and current reference can be started at 43 ns at a minimum supply voltage of 1.35 V. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 ?W at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ oC in the temperature range from 0oC to 100oC and 12.8 ppm/ oC from 30oC to 100oC. The current TC is 119.2 ppm/ oC at temperatures of 0oC to 100oC. Measurement results demonstrate that when the temperature is above 30oC a stable voltage reference can be generated, while a constant current reference is generated at temperature below 70oC.
Secondly, this dissertation presents the design and implementation of the switched-current delta-sigma modulator (DSM), which is fabricated using TSMC 0.18-μm CMOS technology. The fully differential third-order (2-1) switched-current (SI) cascaded delta-sigma modulator takes advantages of an analog error cancellation logic circuit and a digital decimation filter. Besides, a third-order multi-bit switched-current delta-sigma modulator with 4-bit SC flash analog-to-digital converter (ADC) and incremental data weighted averaging (IDWA) is considered, too. In those DSMs, the proposed differential sample-and-hold circuit performs with low input impedance due to feedback and width-length adjustment in SI feedback memory cell (FMC); and that a coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate the error of the current mirror.
Notice that the 2-1 architecture with only the quantizer input being fed into the second stage is introduced not only to reduce the circuit complexity, but also to be implemented easily is using the switched-current approach. Measurements reveal that the dominant error is the quantization error of the second one-bit quantizer (e2). This error can be eliminated using an analog error cancellation logic circuit. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption and chip size are 67.3 dB, 69 dB, 10.9 bits, 12.3 mW, and 0.20 × 0.21 mm2, respectively, with a bandwidth of 40 kHz, a sampling rate of 10.24 MHz, an OSR of 128 and a supply voltage of 1.8 V.
Finally, a third-order multi-bit switched-current delta-sigma modulator is designed with TSMC 0.18-µm 1P6M CMOS process. In the modulator, the 4-bit SC flash ADC improves resolution and IDWA are employed. In order to reduce the digital-to-analog converter (DAC) nonlinearity, the incremental data weighted averaging can achieve first-order DAC noise shaping moving the noise out of the signal band. Also, measurements indicate that the signal-to-noise ratio, dynamic range, effective number of bits, power consumption and chip size are 60.87 dB, 60 dB, 9.82 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz (signal bandwidth 5 kHz ~ 25 kHz), a sampling rate of 10.24 MHz, an OSR of 256 and a supply voltage of 1.8 V.

中文摘要 i
Abstract iii
Acknowledgments v
Table of Contents vi
List of Tables viii
List of Figures ix
Chapter 1 Introduction 1
1.1 Research Motivation 1
1.2 Thesis Organization 4
Chapter 2 A Resistor-Compensation Technique for CMOS Bandgap
and Current Reference with Simplified Start-Up Circuit 5
2.1 Introduction 5
2.2 Circuit Design for Bandgap and Current Reference 6
2.2.1 Basic Principles of CMOS Bandgap Reference 6
2.2.2 Proposed Resistor-Compensation Circuit 7
2.2.3 Proposed Start-Up Circuit 12
2.3 Measured Results 14
2.4 Summary 18
Chapter 3 A Third-Order Switched-Current Delta-Sigma Modulator
with Analog Error Cancellation Logic and Digital Comb Filter 19
3.1 Introduction 19
3.2 Third-Order Delta-Sigma Modulator Topology 21
3.3 Circuit Implementations of Third-Order DSM and Error
Cancellation Logic 23
3.3.1 Current-Mode Sample-and-Hold Circuit 24
3.3.2 Analog Error Cancellation Logic Circuit 29
3.4 Simulated and Measured Results 31
3.5 Summary 37
Chapter 4 A Third-Order Multi-Bit Switched-Current Delta-Sigma
Modulator with Four-Bit Switched-Capacitor Flash ADC and
IDWA 39
4.1 Introduction 39
4.2 Third-Order Multi-Bit SI DSM Structure 41
4.3 Circuit Implementations of Third-Order Multi-Bit Switched-
Current DSM 42
4.3.1 Switched-Current Integrator Circuit 42
4.3.1.1 Current-Mode Sample-and-Hold Circuit 42
4.3.1.2 Switched-Current Integrator Circuit 45
4.3.2 Four-Bit SC Flash Analog-to-Digital Converter 49
4.3.2.1 Improved Flash ADC 49
4.3.2.2 Steady Reference Voltage 51
4.3.2.3 Improved Fully Differential Dynamic Comparator 53
4.3.2.4 Dynamic and Static Parameters Simulation of
Flash ADC 55
4.3.3 Dynamic Element Matching 58
4.3.3.1 Manchester Adder 59
4.3.3.2 Improved Incremental Data Weighted Averaging 61
4.3.4 Current-Mode Digital-to-Analog Converter 65
4.3.5 I-V Converter 68
4.3.6 Bias Current Generator 69
4.3.7 Clock Generator 70
4.4 Simulated Results 71
4.5 Test Setup and Measured Results 74
4.5.1 Test Setup 74
4.5.2 DUT Printed Circuit Board 75
4.5.3 Measured Results 78
4.6 Summary 81
Chapter 5 Conclusions and Future Works 83
5.1 Conclusions 83
5.2 Future Works 85
References 86

1.X. Guan, A. Wang, A. Ishikawa, S. Tamura, Z. Wang and C. Zhang, “A 3V 110?W 3.1ppm/ oC curvature-compensated CMOS bandgap reference,” IEEE Int. Symp. Circuits Sys., Island of Kos, Greece, 2006, pp. 2861-2864.
2.K. N. Leung, P. K. T. Mok and C.Y. Leung, “A 2-V 23-?A 5.3-ppm/oC curvature-compensated CMOS bandgap voltage reference,” IEEE J. of Solid-State Circuits, vol. 38, no. 3, 2003, pp. 561-564.
3.J. M. Audy, “Bandgap voltage reference circuit and method with low TCR resistor in parallel with high TCR and in series with low TCR portions of tail resistor,” U.S. Patent 5291122, Mar. 1, 1994.
4.P. Malcovati, F. Maloberti, C. Fiocchi, and M. Pruzzi “Curvature-compensated BiCMOS bandgap with 1-V supply voltage,” IEEE J. of Solid-State Circuits, vo1. 36, no. 7, 2001, pp. l076-1081.
5.J. Chen and B. Shi, “1 V CMOS current reference with 50 ppm/oC temperature coefficient,” Electronics Letters, vol. 39, no. 2, 2003, pp.209-210.
6.D.-O. Han, J.-H. Kim and N.-H. Kim, “Design of bandgap reference and current reference generator with low supply voltage,” 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, 2008, pp. 1733–1736.
7.T. V. Cao, D. T. Wisland, T. S. Lande, F. Moradi and Y. H. Kim, “Novel start-up circuit with enhanced power-up characteristic for bandgap references,” IEEE Int. SOC Conference, Newport Beach, CA, 2008, pp. 123-126.
8.G. Fahmy, D. Kanemoto, H. Kanaya, K. Yoshida, R. Pokhard, and A. Anand, “A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18?m CMOS,” IEICE Electronics Express, vol. 8, no. 15, 2011, pp. 1204-1209.
9.G.-M. Sung, C.-P. Yu, and D.-A. Yao, “A comparison of second-order sigma-delta modulator between switched-capacitor and switched-current techniques,” IEEE Asia Pacific Conference on Circuits and Systems, Macao, 2008, pp. 1172-1175.
10.J. M. de la Rosa, B. Perez-Verdu, F. Medeiro, R. del Rio, and A. Rodriguez- Vazquez, “Analysis of error mechanism in switched-current sigma-delta modulators,” Analog Integrated Circuits and Signal Proceeding, vol. 38, 2004, pp. 175-201.
11.C. Wang, “An approach to an efficient reduction of the switching noise in switched-current circuits,” IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, 2005, pp. 3127-3130.
12.M.-C. Tsai, A Third-Order Multi-Bit Continuous-Time Delta-Sigma Modulator with Incremental Data Weighted Averaging, Master Thesis, National Taiwan University, Taipei, Taiwan, 2007.
13.H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui, “A CMOS bandgap voltage reference circuit with sub-1-V operation,” IEEE J. of Solid-State Circuits, vol. 34, no. 5, 1999, pp. 670–674.
14.G. Giustolisi, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE J. of Solid-State Circuits, vol. 38, no. 1, 2003, pp. 151–154.
15.M.-D. Ker and J.-S. Chen, “New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 8, 2006, pp. 667–671.
16.X. Xing, Z. Wang and D. Li, “A low voltage high precision CMOS bandgap reference,” Norchip, Aalborg, 2007, pp. l-4.
17.K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/ oC CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE J. of Solid-State Circuits, vol. 37, no. 4, 2002, pp. 526-530.
18.B. Razavi, Design of Analog CMOS Integrated Circuit, U.S.A.: McGraw-Hill College, 2001.
19.P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, U.S.A.: Oxford University Press, 2002.
20.D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York: John Wiley & Sons Inc, 1996.
21.W. Wu, W. Zhiping and Z. Yongxue, “An improved CMOS bandgap reference with self-biased cascoded current mirrors,” IEEE Conf. on Electron Devices and Solid-State Circuits, Tainan, Taiwan, 2007, pp. 945-948.
22.J. P. M. Brito, H. Klimach and S. Bampi, “A design methodology for matching improvement in bandgap references,” 8th Int. Symp. on Quality Electronic Design, San Jose, CA , 2007, pp. 586-594.
23.M. D. Ker, J. S. Chen and C. Y. Chu, “A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device,” IEICE Trans. Electronic, vol. E88-C, no. 11, 2005, pp. 2150-2155.
24.A. Bendali and Y. Audet, “A 1-V CMOS current reference with temperature and process compensation,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 54, no. 7, 2007, pp.1424-1429.
25.S. Amornwongpeeti, M. Ekpanyapong, and C. Punyasai, “A comparative analysis of behavioral simulation for third-order cascaded multi-bit Delta-Sigma modulator with interstage feedback paths,” Int. Conf. on Electrical Engineering/Electronics Computer Telecommunications and Information Technology, Chaing Mai, 2010, pp. 371-375.
26.P. Torkzadeh, J. Javidan, M. Atarodi, and N. Anabtawi, “An elaborate design and implementation of a 3rd order sigma-delta modulator ADC for wideband signals,” 4th IEEE Int. Conf. on Circuits and Systems for Communications, Shanghai, 2008, pp.576-579,.
27.H. Zare-Hoseini, I. Kale, and O. Shoaei, “Modeling of switched-capacitor delta-sigma modulators in SIMULINK,” IEEE Trans. on Instrumentation and Measurement, vol.54, no. 4, 2005, pp. 1646-1654.
28.N. Tan, Switched-Current Design and Implementation of Oversampling A/D Converters, Boston: Kluwer Academic Publisher, 1997.
29.J. B. Hughes and K. W. Moulding, “S2I: a two-step approach to switched- currents,” IEEE Int. Symp. on Circuits and Systems, Chicago, IL, 1993, pp. 1235-1238.
30.G. Jovanovic-Dolecek, Multirate Systems: Design and Applications, Hershey: Idea Group Pub., 2002.
31.G. J. Dolecek and M. Laddomada, “Comb-cosine prefilter based decimation filter”, IEEE Int. Conf. on Industrial Technology, Vi a del Mar, 2010, pp. 205-210.
32.X. Liu and A. N. Willson, Jr “A 1.2 Gb/s recursive polyphase cascaded integrator -comb prefilter for high speed digital decimation filter in 0.18-μm CMOS,” IEEE Int. Symp. on Circuits and Systems, Paris, 2010, pp. 2115-2118.
33.S. Parameswaran and N. Krishnapura, “A 100 µW decimator for a 16 bit 24 kHz bandwidth audio ΔΣ modulator,” IEEE Int. Symp. on Circuits and Systems, Paris, 2010, pp. 2410-2413.
34.Y. Cui, J. Huang, L. Wu, X. Cui, and D. Yu, “An optimized design for a decimation filter and implementation for sigma-delta ADC,” IEEE Int. Conf. of Electron Devices and Solid-State Circuits, Xi’an, 2009, pp. 338-341.
35.D. B. Riber, “A comparison of modulator networks for high-order oversampled ΔΣ analog-to-digital converters,” IEEE Trans. on Circuits and Systems, vol. 38, no. 2, 1991, pp. 145-159.
36.A. Y. Kwentus, Z. Jiang, and A. N. Willson, Jr, “Application of filter sharpening to cascaded integrator-comb decimation filters,” IEEE Transactions on Signal Processing, vol. 45, no. 2, 1997, pp. 457-467.
37.G.-M. Sung and H.-Y. Hsieh, “An ASIC design for decimation filter with canonic signed-digit representation,” Int. Symp. on Intelligent Signal Processing and Communications Systems, Bangkok, 2009, pp. 1-4.
38.Y. C. Lim, R. Yang, D. Li, and J. Song, “Signed-powers-of-two term allocation scheme for the design of digital filters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 5, 1999, pp. 577-584.
39.M. Martinez-peiro, E. I. Boemo, and L. Wanhammar, “Design of high-Speed multiplierless filters using a nonrecursive signed common subexpression algorithm,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 3, 2002, pp. 196-203.
40.G. Nikandish, B. Sedighi and M. S. Bakhtiar, “Performance comparison of switched-capacitor and switched-current pipeline ADCs,” IEEE Int. Symp. on Circuits and Systems, New Orleans, LA, 2007, pp. 2252–2255.
41.G.-M. Sung, C.-P. Yu and Y.-H. Hou “High-order delta-sigma modulator with switched-current feedback memory cell,” IEEE Asia Pacific Conference on Circuits and Systems, Macao, 2008, pp.1148-1151.
42.N. Tan, “Switched-current oversampling converters,” IEEE Circuits and Devices Magazine, vol. 11, no. 1, 1995, pp. 36-38.
43.M. G. Kim, G.-C. Ahn, P. K. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You, J.-W. Kim, G. C. Temes, and U.-K. Moon, “A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, 2008, pp. 1195-1206.
44.C. A. Prior and C. R. Rodrigues, “A switched current sigma delta modulator using a low distortion feedfoward topology,” 53rd IEEE Int. Midwest Symp. on Circuits and Systems, Seattle, WA, 2010, pp.296–299.
45.C.-J. Cheng and S.-Y. Lee, “A low-voltage adaptive switched-current SDM for bio-acquisition microsystems,” IEEE Int. Symp. on Circuits and Systems, Island of Kos, 2006, pp.341-344.
46.Y. Aiba, K. Tomioka, Y. Nakashima, K. Hamashita and B.-S. Song, “A fifth-order Gm-C continuous-time ΔΣ modulator with process-insensitive input linear range,” IEEE Journal of Solid-State Circuits, vol. 44, no. 9, 2009, pp. 2381-2391.
47.K. Kang, J. Roh, Y. Choi, H. Roh, H. Nam, and S. Lee, “Class-D audio amplifier using 1-bit fourth-order delta-sigma modulation,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 55, no. 8, 2008, pp. 728-732.
48.B. Razavi, Principles of Data Conversion System Design, New York: John Wiley & Sons, 1995.
49.H. Lee, Digital Error-Averaging Technique for Pipelined Analog to Digital Converter, Master Thesis, National Taiwan University, Taipei, Taiwan, 2002.
50.Y. Geerts, M. Steyaert and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Boston: Klower Academic Publishers, 2002.
51.K.-D. Chen, Automatic Coefficients Synthesis and Circuit Implementation Techniques for High-Order Sigma-Delta Modulator, Ph. D. Thesis, National Cheng Kung University, Tainan, Taiwan, 1999.
52.T.-H. Kuo, K.-D. Chen and H.-R. Yeng, “A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE Journal Solid-State Circuits, vol. 37, no. 1, 2002, pp.11–17.
53.M.-C. Tsai and T.-H. Lin, “Design of a continuous-time 3rd-order delta-sigma modulator with incremental data weighted averaging,” International Journal of Electrical Engineering, vol. 14, no. 3, 2007, pp. 157-165.
54.C.-T. Wu, The Design of a High Speed Pipelined Analog-to-Digital Converter, Master Thesis, National Taiwan Ocean University, Keelung, Taiwan, 2004.
55.R. J. Baker, H. W. Li, and D. E. Boyce, “CMOS Circuit Design, Layout, and Simulation”, New York: John Wiley & Sons, 1997.