臺灣博碩士論文加值系統

本論文提出一種利用MEMS壓力計感測元件，將測得之訊號直接傳入相連的CMOS訊號處理單元中，此訊號處理單元可為電容量測單元，因此能夠直接量測、判斷所測得的極微小電容(femto level)訊號變化。後階段可利用MEMS壓力計陣列形式，以提高不同的壓力感測範圍，以發揮電容感測器的辨識能力，實現可穿戴式（Wearable）或植入式(implantable)單晶片（SoC）之目的。
由於MEMS壓力計在感測壓力時，電容訊號變化大部分為1~200fF等級，利用訊號讀取電路做偵測，再利用公式推算出微結構的初始電容值和電容變化值。於電容訊號感測方面，本研究利用積分器將感測電容變化訊號轉換成電壓訊號，再藉由儀表放大器作為訊號放大及讀出電路。經由儀表放大器結構，提供可調增益和良好抑制雜訊能力。訊號的共模輸入雜訊可以經由儀表放大器給消除掉而不會被放大。本系統以TSMC 0.35 μm 2P4M製程來設計感測晶片，晶片面積為2.500*2.482 mm2 ，工作電壓採用3.0V，以輸入1 MHz載波測試，可以感測範圍約數十fF~數百fF之電容值。因此本研究系統確實可有效感測到微量電容變化。

In this thesis, a new type of capacitor sensor composed of pressure and CMOS circuitry is proposed. The capacitor variation can be measured directly by means of the sensing circuit, which is composed of an impedance amplifier or a switched-capacitor amplifier. The goal of this sensor is to detect various blood vessel pressures. It also provides an effective way in applications of bio-sensors. Furthermore, an array-typed MEMS-Pressure sensor can be to detect blood vessel pressures in various pressure ranges, and it is desired to become a wearable or implantable device.
The sensing capacitor range of the proposed sensor is about 1~200 fF. By using readout circuits and comparing the I/O waveforms (in sine wave), we can calculate the capacitor variation of MEMS-Pressure sensor. We converted the Pressure-Sensor output capacitance into a voltage by a convert in this study. The sensing signals are then amplified and readout with instrumentation amplifier (IA) circuit. The proposed system is implemented in TSMC 0.35 μm 2P4M technology. The chip area is roughly 2.500*2.482 with power supply of 3.0V. The input signal is 1 MHz sine waves. The proposed structure has a capacitance measuring range from 1 femto-farad to hundreds of femto-farad. This study successfully presents a smart sensor which can detect a very small capacitance variation of MEMS-Pressure sensor.

摘要 i
ABSTRACT ii
誌謝 iii
目 錄 iii
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究背景與動機 2
1.2 論文架構 6
第二章 感測器與放大器原理簡介 7
2.1 感測系統簡介 7
2.2 四種不同的放大器形式 14
2.3 運算放大器 18
第三章 系統架構與運算放大器設計 24
3.1 本論文電路之系統概述 24
3.2 最佳化運算放大器設計方法 27
3.3 運算放大器架構 32
3.4 雙級運算放大器架構 33
3.5 折疊運算放大器 35
3.6 切換電容式放大器電路設計與分析 41
3.7 相關雙取樣電路 51
3.8 取樣且保持 54
3.9 時脈延遲電路 54
3.10 儀表放大器 56
第四章 模擬結果 58
4.1 前言 58
4.2 兩級運算放大器電路模擬結果 59
4.3 折疊運算放大器電路模擬結果 64
4.4 C TO V前級大電阻模擬結果 71
4.5 非重疊時脈訊號模擬結果 72
4.6 整體感測電路前後模擬結果 74
第五章 電容感測器佈局與量測 77
5.1 電路佈局與考量 77
5.2 量測佈局與考量 80
5.3 電路量測結果 81
第六章 結論與未來展望 87
參考文獻 89
附錄A 91

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