臺灣博碩士論文加值系統

本論文主要的研究重點在於生醫前端電路上低功率消耗和提高電路效能。低功率消耗和低雜訊的發展變成在生醫應用的目標。而用於生醫系統之計錄器，如ECG/EEG等記錄器，其效能相當依賴系統中的儀表放大器。儀表放大器功用在於將微小的信號放大到較大的信號。然而，這些系統相當容易受到雜訊和共模電壓受到干擾，這是因為雜訊通常都大於輸入信號。在傳統的電路上，電流式儀表放大器有較好的共模拒斥比來抵抗雜訊，但是卻有較高的閃爍雜訊。另一方面在電路中電流鏡不匹配也會造成共模拒斥比下降。
在此論文中，以差動差分傳輸器來實現電流式儀表放大器，同時加入截波技術來消除來自閃爍雜訊的干擾。並且在電流式電路之電流鏡映射上使用疊接方式來降低共模電壓干擾。除此之外，電流式儀表放大器的高輸入阻抗可以降低負載效應。之後，由交換式電容電路組成的二階低通濾器來濾除頻寬外的雜訊，再用二階三角積分調變器做信號處理。以上三個電路中採用台積電0.35微米2P4M的製程技術在供應電壓±0.9V來完成。

This thesis is focused on investigating the low power consumption in biomedical front-end circuit; besides, performance of the circuit has been raise. The development of low power and low noise design has become the focus of biomedical applications. The performance of biomedical recording system depends on the instrumentation amplifier, such as Electrocardiogram or Electroencephalogram recording. It is to amplify very small voltage signal to large voltage amplitudes; nonetheless, the system is sensitively associated with noise and common-mode voltage because of these signals are usually greater than input signal. In traditional circuits, the current-mode instrumentation amplifier (CMIA) has the advantage for high CMRR performance, but it exhibits high significantly 1/f noise. On the other hand, the current mirror of the CMIA is mismatch and will be lower the CMRR.
In this thesis, CMIA using differential difference current conveyor, the interference of noise from 1/f noise can be removed by chopper-stabilized technology. The interference of common-mode voltage is reduced by the current-mode circuit that uses the cascode current mirror. Besides, the load effect is reduced by the high input impedance of the CMIA. The signal outside the bandwidth is removed by second order low-pass filter using switched-capacitor circuit, and the inner bandwidth counterpart is processed by second order sigma-delta modulator. For three circuits above, whose power supplies are ±0.9V, is implemented using TSMC 0.35um process.

中文摘要 i
英文摘要 ii
目錄 iii
圖目錄 vi
表目錄 xi

第一章 序論 1
1.1 相關研究與發展現況 1
1.2 研究動機與目的 2
1.3 論文架構 2

第二章 低雜訊低偏移電壓技術 4
2.1 基本簡介 4
2.2 CMOS運算放大器雜訊分析 4
2.2.1 雜訊來源 4
2.2.2 雜訊頻寬 7
2.3 自動歸零技術 8
2.4 截波穩定技術 8
2.4.1 基本原理 8
2.4.2 調變流程 9
2.4.3 截波在電路的影響 10
2.4.4 剩餘偏移電壓 12
2.5 CMOS開關非理想效應 15
2.5.1 時脈饋入 15
2.5.2 通道電荷注入 16
2.5.3 取樣雜訊和漏電流 16
2.5.4 降低非理想效應 17

第三章 生醫前端電路設計 20
3.1 基本簡介 20
3.2 電流式儀表放大器 21
3.2.1 電流傳輸器和差動差分電流傳輸器說明 21
3.2.2 電流式儀表放大器說明 22
3.2.3 新型電流式儀表放大器 25
3.2.4 時脈產生器 29
3.3 截波穩定型運算放大器設計 31
3.3.1 基本架構介紹 31
3.3.2 截波式放大器 31
3.3.3 雜訊考量 32
3.3.4 交叉前饋反向巢式米勒補償法 33
3.4 模擬結果 36
3.4.1 運算放大器模擬結果 36
3.4.2 儀表放大器模擬結果 38
3.5 晶片佈局圖 42
3.6 應用於生醫系統之儀表放大器比較 43

第四章 低通濾波器和三角積分調變器設計 44
4.1 低通濾波器 44
4.1.1 基本架構介紹 44
4.1.2 交換式可調二階低通濾波器 45
4.1.3 線性轉導放大器 48
4.1.4 低電壓線性轉導放大器 49
4.1.5 duty-cycle產生器 50
4.1.6 倍壓電路 52
4.1.7 模擬結果 54
4.1.8 晶片佈局圖 58
4.2 三角積分調變器 59
4.2.1 三角積分調變器之原理 59
4.2.1.1 奈奎氏取樣定理 59
4.2.1.2 超取樣原理 60
4.2.1.3 量化誤差 61
4.2.1.4 雜訊移頻技術 63
4.2.2 二階三角積分調變器之架構 65
4.2.2.1 一階三角積分調變器 65
4.2.2.2 二階三角積分調變器 67
4.2.2.3 高階三角積分調變器 69
4.2.3 二階三角積分調變器之電路設計 69
4.2.3.1 系統行為模擬 70
4.2.3.2 運算放大器 74
4.2.3.3 開關電容式積分器 74
4.2.3.4 一位元比較器 77
4.2.3.5 數位類比轉換器 78
4.2.3.6 二階三角積分調變器 79
4.2.4 模擬結果 80
4.2.5 晶片佈局圖 84

第五章 量測結果 85
5.1 量測環境與方法 85
5.2 儀表放大器之量測結果 85
5.3 濾波器之量測結果 88
5.4 整合儀表放大器和濾波器之量測結果 93

第六章 結論與未來研究方向 95
6.1 結論 95
6.2 未來展望 96

參考文獻 97

[1] C. C. Enz, E. A. Vittoz, and F. Krummenacher,〝A CMOS Chopper Amplifier,” IEEE J. Solid-State Circuit, Vol. sc-22, No. 3, pp.335-342, Jun. 1987.
[2] C. C. Enz and G. C, “Circuit Techniques For Reducing The Effects Of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, And Chopper Stabilization,” Proceedings Of The IEEE Vol. 84, NO. 11, pp.1584-1614, 1996.
[3] C. Menolf and Q. Huang,〝A Low-Noise CMOS Instrumentation Amplifier For Thermoelectric Infrared Detectors,” IEEE J. Solid-State Circuit, Vol. 32, No. 7, pp.968-976, Jul. 1997.
[4] A. Bakker, K. Thiele, and J. H. Huijsing,〝A CMOS Nested-Chopper Instrumentation Amplifier With 100-nV Offset,” IEEE J. Solid-State Circuit, Vol. 35, No. 12, pp.1877-1883, DEC. 2000.
[5] B. Razavi, “Design of Analog CMOS Integrated Circuit,” McGraw Hill, International Edition, 2001.
[6] "BSIM3v3.3.2.2 MOSFET Model Users’ Manual,“ BSIM Reserved Group, Department Electrical Engineering Computer Sciences, University of California 1999.
[7] J. M. Rabaey, A. Chandrakasan, and B. Nikonlic, Digital Integrated Circuits: A design Perspective, ed. Upper Saddle River, Prentice-Hall, 2001
[8] A. Harb and M. Sawan, “Low-Power CMOS Interface For Recording And Processing Very Low Amplitude Signals,” Analog Integrated Circuits and Signal Processing, vol.39, NO. 1, pp.39-54, Apr. 2004.
[9] M. Shojaei-Baghini, R. K. Lal, and D. K. Sjarma, “A low-Power And Compact Analog Cmos Processing Chip For Portable ECG Recorders” IEEE Asian Solid-State Circuits Conference, 2005, pp.473-476.
[10] 黃照宏，以電流式主動元件為基礎之濾波器與振盪器的設計與實現，碩士論文，國立台北科技大學電腦與通訊研究所，台北，2007.
[11] 李榮彬，以差動差分電流傳輸器設計高階主動濾波器及其應用，碩士論文，國立台北科技大學電腦與通訊研究所，台北，2006.

[12] B .Wilson,〝Universal Conveyor Instrumentation Amplifier” IEEE Trans. On Instrumentation And Measurement, Vol.25, NO. 7, pp.470-471, 1989.
[13] T. Kaulberg, 〝A CMOS Current-Mode Instrumentation Amplifier,” IEEE J.Solid-State Circuits, Vol.28, NO. 7, pp.849-852, 1993.
[14] A. A. Khan, M. A. Al-Turaigi, and M. A. El-Ela,〝An Improved Current-Mode Instrumentation Amplifier With Bandwidth Independent Of Gain,” IEEE Trans. On Instrumentation And Measurement, Vol.44, NO. 4, Aug. 1995.
[15] S. J. G. Gift,〝An Enhanced Current-Mode Instrumentation Amplifier” IEEE Trans. On Instrumentation And Measurement, Vol.50, NO. 1, pp.85-88, Jan.2001.
[16] J. Hu, Y. Xia, T. Xu, and H. Dong, 〝A New CMOS Differential Difference Current Conveyor And Its Applications,” 2004 International Conference on Communications, Circuits and Systems, Vol. 2, 2004, pp.1156-1060.
[17] T. Dension, K. Consoer, A. Hachenburg, and W. Santa, 〝A 2.2uW 94nv/√Hz, Chopper -Stabilized Instrumentation Amplifier For EEG Detection In Chronic Implants,” IEEE International Solid-State Circuits Conference, Dig. Tech, Papers, 2007, pp.162-594.
[18] R.F. Yazicioglu, 〝A 60uW 60nV/√Hz Readout Front-End For Portable Biopotential Acquistion Systems,” IEEE International Solid-State Circuits Conference, Dig. Tech, Papers, 2006, pp.1100-1110.
[19] A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, 〝Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer And Resistor,” IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 54, No. 5, pp.382-384, May. 2007.
[21] K. N. Leung and P. K. T. Mok,〝Analysis of Multistage Amplifier –Frequency Compensation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., Vol. 48, No. 9, pp.1041-1056 Sep. 2001.
[22] G. Palumbo and S. Pennisi , ”Design Methodology And Advances In Nested-Miller Compensation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., Vol. 49, No. 2, pp.893-903, Jul. 2002.
[23] H. Lee and P. K. T. Mok,〝Advances In Active-Feedback Frequency
Compensation With Power Optimization And Transient Improvement,” IEEE Trans. Circuits Syst. I, Regular Papers, Vol. 51, No. 9, pp.1690-1696, Sep. 2002.
[24] H. Lee and P. K. T. Mok,〝A Low-Dropout Regulator For SoC With Q-Reduction,” IEEE J. Solid-State Circuit, Vol. 42, No. 3, pp.658-664, Mar. 2007.
[25] X. Peng and W. Sansen,〝AC Boosting Compensation Scheme For Low-Power Multistage Amplifiers,” IEEE J. Solid-State Circuit, Vol. 39, No. 11, pp.2074-2079, Nov. 2007.
[26] K. A. Ng and P.K. Chan,〝A CMOS Analog Front-End IC For Portable EEG/ECG Monitoring Applications” IEEE Trans. Circuits Syst. I, Regular Papers, Vol.52, No. 11, pp.5335-5347, Nov. 2005.
[27] A. Veeravalli, E. Sanchez-Sinencio, and J. Silva-Martinez, “Transconductance Amplifier Structures With Very Small Transconductances: A comparative Design Approach,” IEEE J. Solid-State Circuits, Vol. 37, NO. 6, pp.770-775, Jun. 2002.
[28] P. Kurahashi, P. K. Hanumolu, G. C. Temes, and U. K. Moon, “Design Of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters,” IEEE J. Solid-State Circuits, Vol. 42, NO. 6, pp.1699-1709, Aug. 2007.
[29] A. Demomsthenous and M. Panovic, “Low-Voltage MOS Linear Tranconductor/Squarer And Four-Quadrant Multiplier For Analog VLSI,” IEEE Trans. Circuits Syst. I, Regular Papers, Vol. 52, NO. 9, pp.1721-1731, Sep. 2005.
[30] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V Analog Circuit Techniques And Their Application In OTA And Filter Design,” IEEE J. Solid-State Circuits, Vol. 42, NO. 6, pp.2373-2387, Dec. 2005.
[32] 楊盛惟，應用於數位音頻系統之微功率開關電容三階三角積分調變器設計，碩士論文，國立台北科技大學電腦與通訊研究所，台北，2007.
[33] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, 1997.
[34] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[35] S.Y. Lee and C.J. Cheng,〝A Low-Voltage And Low-Power Adaptive Switched-Current Sigma–Delta ADC For Bio-Acquisition Microsystems” IEEE Trans. Circuits Syst. I, Regular Papers, Vol.53, No. 12, pp.2628-2636, Dec. 2006.
[36] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford, 2002.
[37] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press Wiley Interscience 2005.
[38] R. Schreier, The Delta-Sigma toolbox for Matlab, Oregon State University. [Online]. Available: http://www.mathworks.com/matlabcentral/fileexchange/