臺灣博碩士論文加值系統

本篇論文探討之反相器有別於傳統CMOS反相器，此反相器為垂直式結構稱為CFET，使用Monolithic的製程技術，n型薄膜電晶體為下層元件、p型薄膜電晶體為上層元件，相對於傳統CMOS節省了一半的面積，但同時也使製程難度大幅提升。
本篇論文調變元件的通道厚度、閘極氧化層、通道長度，並分析其電性的差異，通道厚度越薄VTH往大電壓平移、S.S.較佳、ION劣化，VTH與ION劣化歸因於晶界的缺陷影響，S.S.較佳歸因於閘極控制能力上升；閘極氧化層越薄VTH往小電壓平移、S.S.較佳、ION較高，因為閘極氧化層越薄，閘極控制能力較佳，使元件提早開啟VTH下降、S.S.與ION較佳；微縮通道長度VTH往小電壓平移、S.S.劣化、ION上升，元件提早開啟和ION較高與晶界的缺陷有關，S.S.劣化較為嚴重與閘極控制能力相關。
反相器的特性與元件微縮息息相關，微縮通道厚度與閘極氧化層厚度，使反相器切換電壓、Gain皆改善；微縮通道長度，使反相器切換電壓改善、Gain不變。本篇論文探討反相器特性分為的五區，分別代表了兩顆電晶體不同的開關狀態，A：n型薄膜電晶體截止區、p型薄膜電晶體線性區；B：n型薄膜電晶體截止區、p型薄膜電晶體型飽和區；C：n型薄膜電晶體飽和區、p型薄膜電晶體線性區；E：n型薄膜電晶體飽和區、p型薄膜電晶體飽和區；D：n型薄膜電晶體線性區，p型薄膜電晶體飽和區。

The inverter discussed in this paper is different from the traditional CMOS inverter. This inverter is a vertical structure called CFET. It uses Monolithic process technology. The n-type thin film transistor is the bottom device and the p-type thin film transistor is top device saves half the area compared to conventional CMOS, but it also greatly increases the process difficulty.
In this paper, the channel thickness, gate oxide layer and channel length of the modulation component are analyzed, and the difference in electrical properties is analyzed. The thinner the channel thickness is, the VTH is shifted to large voltage, the S.S. is better, the ION is degraded, and the VTH and ION degradation are attributed to influence of defects in the grain boundary, S.S. is better attributed to the increase of gate control ability; Thinner the gate oxide layer, the VTH is shift to the small voltage, the S.S. is better, the ION is higher, are attributed to the gate control ability; The channel length effect VTH is shifted to a small voltage, the S.S. is degraded, the ION is increased, so device is opened earlier, and the ION is higher attributed to defect of the grain boundary, and the S.S. degradation is attributed to gate control ability.
The characteristics of the inverter are closely related to the small scale of the device. The thickness of the microchannel and the thickness of the gate oxide layer improve the inverter switching voltage and Gain. The length of the microchannel shortens the switching voltage of the inverter and the Gain does not change. This paper discusses the five regions of the inverter characteristics, which represent the different switching states of the two transistors, A: n-type thin film transistor cut-off region, p-type thin film transistor linear region; B: n-type thin film transistor cut-off region, p-type thin film transistor saturation region; C: n-type thin film transistor saturation region, p-type thin film transistor linear region; E: n-type thin film transistor saturation region, p-type thin film transistor saturation region; D : n-type thin film transistor linear region, p-type thin film transistor saturation region.

論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 vi
圖目錄 viii
表目錄 xii
第 一 章 緒論 1
1.1 前言 1
1.2 關於矽的介紹 2
1.2.1 原子的排列 2
1.2.2 晶向介紹 3
1.2.3 原子排列與雜質缺陷 3
1.3 多晶矽薄膜電晶體（Poly-Si Thin Film Transistor, Poly-Si TFT） 3
1.4 短通道效應 （Short Channel Effect, SCE） 4
1.4.1 汲極誘發能障降低（Drain-Induced Barrier Lowering, DIBL） 5
1.4.2 臨界電壓滾降 （Threshold Voltage Roll-Off） 5
1.4.3 擊穿崩潰 （Punch Through） 5
1.5 閘極誘發汲極漏電（Gate induced Drain leakage, GIDL） 5
1.6 多晶矽薄膜電晶體漏電機制所帶來的影響 6
1.7 多閘極電晶體（Mulitgate Device） 6
1.8 互補式薄膜電晶體（Complementary Film Effect Transistor, CFET） 6
1.9 實驗動機 8
第 二 章 實驗步驟與流程 18
2.1 CFET元件製程 18
2.2 CFET電性參數萃取 20
2.2.1平帶電壓（Flatband Voltage, VFB） 20
2.2.2臨界電壓（Threshold Voltage, VTH） 20
2.2.3次臨界擺幅（Subthreshold Swing, S.S.） 20
2.2.4轉導（Transconductance, gm） 20
2.2.5開啟狀態電流（On State Current, ION） 21
2.2.6關閉狀態電流（Off State Current, IOFF） 21
2.2.7界面陷阱能態（Interface Trap State, Nit） 21
2.2.8晶粒邊界陷阱能態（Grain Boundary Trap State, NGB） 21
2.2.9電壓放大增益值（Amplifier Voltage Gain, AV） 22
2.2.10通道電阻（Channel Resistance, RCH or RDS） 22
2.3 CFET電性量測方法 22
第 三 章 結果與討論 40
3.1互補式薄膜電晶體通道厚度效應 40
3.2互補式薄膜電晶體閘極氧化層厚度效應 41
3.3互補式薄膜電晶體通道長度效應 42
第 四 章 結論 59
參考文獻 60

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