臺灣博碩士論文加值系統

本篇論文以90 nm CMOS製程來實現全晶片化的Doherty架構功率放大器設計，在其輸出端是以串聯式變壓器來實現一個功率結合器。期望以Doherty架構來達到強化發射機之平均效率的目的，來解決在退讓功率點上效率低落的問題。本篇論文主要分為兩部分，首先第一個部分針對傳統的線性功率放大器做介紹，並且以晶片來實現一個操作頻率為2.4 GHz的 A類線性功率放大器，其功率電晶體架構採用疊接形式設計；另外在放大器部分採用全差動式設計，因此在輸出端與輸入端採用巴倫器來將訊號做差動與單端的轉換，並且達到阻抗匹配的功能。接著在第二個部分則介紹CMOS Doherty功率放大器設計，並且以晶片來實現一個操作頻率為2.4 GHz的CMOS Doherty功率放大器。本篇論文使用到主要放大器及輔助放大器來做功率結合，為了做到Doherty放大器的操作，主與輔助功率放大器分別設計在AB類以及C類；另外在其輸出端的串聯式變壓器為非對稱式的設計，其目的為提高退讓功率點上的功率轉換效率，進而達到提升發射機之平均效率的目的。

This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 章節規劃 8
第二章 CMOS線性功率放大器 9
2.1 線性功率放大器 9
2.1.1 基本設計理論 9
2.1.2 功率放大器設計理論 13
2.1.3 功率放大器分類 18
2.2 晶片電路設計 24
2.2.1 電路架構的選擇與考量 24
2.2.2 設計流程 31
2.2.3 功率放大器設計方法與考量 32
2.2.4 多指狀纏繞式變壓器設計方法與考量 34
2.3 晶片電路模擬與量測結果 38
2.3.1 模擬結果 38
2.3.2 量測方法與儀器設置 40
2.3.3 量測結果討論與檢討 41
第三章 CMOS Doherty功率放大器 47
3.1 Doherty功率放大器 47
3.1.1 Doherty功率放大器理論分析 47
3.1.2 功率結合變壓器理論分析 53
3.2 晶片電路設計 56
3.2.1 架構簡介 56
3.2.2 設計流程 58
3.2.3 放大器設計方法與考量 59
3.2.4 功率結合器設計方法與考量 60
3.2.5 偏壓電路設計方法與考量 62
3.3 晶片電路模擬與量測結果 63
3.3.1 模擬結果 63
3.3.2 量測方法與儀器設置 65
3.3.3 量測結果討論與檢討 66
第四章 結論 67
參考文獻 68

[1]洪茂峰，無線通訊技術的演進，國立成功大學校刊，第220期，29 ~ 33頁。
[2]朱國瑞、呂淑雅、林士雄、李旺龍，微波及微波的應用&;quot;，科學發展， 2005年11月，395期，28~37頁。
[3]Developed Li-Fi Technology – Overview, Available online at http://www.lificonsortium.org/technology.html
[4]Eid Alsabbagh, Haoyang Yu, Kevin Gallagher, “802.11ac design considerations for mobile devices,” Microwave Journal, February 14, 2013.
[5]David Angell, “Intel® Centrino® 802.11n Wi-Fi gets down to business,” Technology@Intel, April 14, 2010.
[6]IEEE 802.11 Working Group, “IEEE 802.11: Wireless LAN medium access control (MAC) and physical layer (PHY) specifications,” IEEE-SA, April, 2012.
[7]Mirin Lew, “Introduction to 802.11ac WLAN technology and testing,” Agilent Technologies webcast slides, Jan, 2012.
[8]Wi-Fi Alliance®, Available online at http://www.wi-fi.org/who-we-are
[9]IEEE 802.15.3a, WPAN High Rate Alternative PHY Task Group 3a (TG3a), Available online at http://www.ieee802.org/15/pub/TG3a.html
[10]IEEE 802.15.1, Available online at https://www.ieee802.org/15/pub/TG1.html
[11]Feng Chen, Nan Wang, Reinhard German, Falko Dressler, “Performance evaluation of IEEE 802.15.4 LR-WPAN for industrial applications,” Wireless on Demand Network Systems and Services, Jan, 2008.
[12]IEEE, “Wireless medium access control (MAC) and physical layer (PHY) specifications for low-rate wireless personal area networks (WPAMs),” IEEE Standard 802.15.4, 2006.
[13]ZigBee Alliance homepage, Available online at http://www.zigbee.org/
[14]張盛富、張嘉展，無線通訊射頻晶片模組設計－射頻晶片篇，台北，全華圖書股份有限公司，2008年。
[15]G. Hanington, P. F. Chen, P. M. Asbeck and L. E. Larson, “High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications,” IEEE Trans. Microw. Theory and Tech., vol. 47, pp. 1471-1476, Aug. 1999.
[16]P. Reynaert and M. Steyaert,”A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2598-2608, Dec. 2005.
[17]F. Wang, D. Kimball, D. Lie, P. Asbeck, and L. Larson, ”A monolithic high-efficiency 2.4-GHz 20-dBm SiGe BiCMOS envelope-tracking OFDM power amplifier,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1271-1281, Jun. 2007.
[18]F. Wang, D. Kimball, J. Popp, A. Yang, D. Lie, P. Asbeck, and L. Larson, ”An improved power-added efficiency 19-dBm hybrid envelope elimination and restoration power amplifier for 802. 11g WLAN applications,” IEEE Trans. Microw. Theory Tech.,” vol. 54, no. 12, pp. 4086-4099, Dec. 2006.
[19]H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. El-Tanani, and K. Soumyanath, “A flip-chip-packaged 25.3 dBm class-D outphasing power amplifier in 32 nm CMOS for WLAN application,” IEEE J. Solid-State Circuits,” vol. 46, no. 7, pp. 1596-1605, Jul. 2011.
[20]W. H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol.24, no. 9, pp. 1163-1182, Sep. 1936.
[21]Steve C. Cripps, “RF Power Amplifier For Wireless Communications,” Artech House, London, 2006.
[22]Behzad Razavi, “RF Microelectronics,” Prentice Hall PTR, USA, pp.149-155, 1997.
[23]E. L. Tan, “Rollett-based single-parameter criteria for unconditional stability of linear two-ports,” IEEE Proc.-Micow. Antennas Propag., vol. 151, no.4, pp. 298-302, August 2004.
[24]ADS, ver. 2011, Agilent Technol., Santa Clara, CA, 2011.
[25]D. M. Pozar, “Microwave Engineering, 3rd Ed,” John Wiley &; Sons, Inc., 2005.
[26]Tzyy-Sheng Horng, “RF communication circuit design,” course slides, 2012.
[27]A. S. Sedra, K. C. Smith, “Microelectronic Circuit, 6th Ed,” Oxford, 2011.
[28]Sowlati, T.; Leenaerts, D. M. W.; “A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier,” IEEE Journal of Solid-State Circuits, Vol 38, Issue 8, Aug. 2003, pp:1318 – 1324.
[29]Chien-Min Lo, Chin-Shen Lin, Huei Wang, “A miniature V-band 3-Stage cascode LNA in 0.13 CMOS,” in Proc. of IEEE International Solid-State Circuits Conference. Tech. Papers, pp. 1254-1263, Feb.6-9, 2006.
[30]C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 823–830, May 2001.
[31]T. Kuo and B. Lusignan, “A 1.5-W class-F RF power amplifier in 0.25- m CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 154–155, 2001.
[32]Behzad Razavi,“ A layout technique for millimeter-wave PA transistors,” IEEE, Radio Frequency Integrated Circuits Symposium (RFIC), pp:1-4, 2011.
[33]Boshi Jin, Junghwan Moon, Chenxi Zhao, Bumman Kim,“ A 30.8-dBm wideband CMOS power amplifier with minimized supply fluctuation,” IEEE Trans. Microwave Theory &; Tech., vol 60, no. 6, pp. 1658-2142, August 2010.
[34]Jongchan Kang, Jehyung Yoon, Kyoungjoon Min, Daekyu Yu, Joongjin Nam, Youngoo Yang, Bumman Kim,“ A highly linear and efficient differential CMOS power amplifier with harmonic control,” IEEE Journal of Solid-State Circuit, vol. 41, no.6, pp. 1314-1322, June, 2012.
[35]魏祖強 平面型變壓器為基礎之積體化被動元件設計與模型化研究，國立中山大學電機工程研究所碩士論文，民國九十七年。
[36]C. Patrick Yue, S. Simon Wong,” On-Chip spiral inductors with patterned ground shields for Si-Based RF IC’s,” IEEE Journal of Solid-State Circuits, vol. 33, no. 5, May, 1998.
[37]HFSS, ver. 11, Ansoft Corp., Pittsburgh, PA, 2008.
[38]Virtuoso, ver.6.1.6, Cadence Corp., San Jose, CA, 2012.
[39]K.J. Kim, T. H. Lim and K.H. Anh,” The novel high efficiency on chip transformers for the CMOS,” IEEE ISIC, pp.401–404, 2009.
[40]Chenxi Zhao, Byungjoon Park, Yunsung Cho, Bumman Kim,” Analysis and design of CMOS doherty power amplifier using voltage combining method,” IEEE International, Wireless Symposium (IWS), 2013.
[41]Naratip Wongkomet, Luns Tee, Paul R. Gray,“ A 31.5 dBm CMOS RF doherty power amplifier for wireless communication.” IEEE Journal of Solid-State Circuit, vol. 41, no. 12, Dec., 2006.
[42]Kyoung-Joon Cho, Wan-Jong Kim, Ji-Yeon Kim, Jong-Heon Kim, Shawn P. Stapleton,” A novel N-way distributed doherty amplifier with improved efficiency at high PAR signals,” Microwave Journal, April 15, 2008.
[43]Li-Yuan Yang, Hsin-Shu Chen, Yi-Jan Chen, “A 2.4 GHz fully integrated cascode-cascade CMOS doherty power amplifier,” IEEE, Microwave and Wireless Components Letters, vol. 18, no. 3, pp. 197-199, Mar, 2008.
[44]M. Elmala, J. Paramesh, K. Soumyanath,” A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion,” IEEE Journal Solid-State Circuits, vol. 41, no. 6, pp 1323-1332, Jun, 2006.
[45]E. Kaymaksut,P. Reynaert,” Transformer-Based uneven doherty power amplifier in 90 nm CMOS for WLAN applications,” IEEE Journal Solid-State Circuits, vol. 47, no. 7, pp. 1659-1671, 2012.
[46]K. H. An et al.,” Power-combing transformer techniques for fully-integrated CMOS power amplifier,” IEEE J. Solid-State Circuit, vol. 43, no. 5, pp. 1064-1075, May 2008.
[47]I. Aoki et al.,” Distributed active transformer – a new power-combining and impedance-transformation technique,” IEEE Trans. Microw. Theory and Tech., vol. 50, no. 1, pp, 316-331, Jan 2002.
[48]E. Kaymaksut, B. Francois and P. Reynaert, “Analysis and Optimization of Transformer-Based Power Combining for Back-Off Efficiency Enhancement”, IEEE Transactions on Circuits and Systems - I, vol. 60, No. 4, pp. 825-835, April 2013.
[49]K. Onizuka, S. Saigusa and S. Otaka, “A +30.5 dBm CMOS Doherty Power Amplifier with Reliability Enhancement Technique”, Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, Hawai, July, 2012.