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研究生:謝仲銘
研究生(外文):Chung-Ming Hsieh
論文名稱:三角積分調變器設計自動化
論文名稱(外文):Sigma Delta Modulator Design Automation
指導教授:邱弘緯邱弘緯引用關係
口試委員:范育成黃育賢黃國威
口試日期:2007-07-04
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:110
中文關鍵詞:三角積分調變器模擬退火演算法最佳化類比電路設計自動化低電壓低功率
外文關鍵詞:sigma delta modulatorsimulated annealing algorithmoptimizationanalog circuit design automationlow power low voltage
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  在這篇論文中我們將sigma delta modulator的自動化設計流程實現出來。自動化設計的流程將分為兩各部份:系統設計及電路設計兩方面。在系統設計自動化方面我們通常使用Matlab Simulink,並且建立了ㄧ些實際電路會產生的非理想效應來使系統模擬更加準確。而電路設計自動化則使用Cadence Spectre和NeoCircuit。接下來使用PERL這個程式語言撰寫控制及連結兩種不同模擬軟體的Script,PERL將會負責整各自動化流程的控制。其中我們應用了模擬退火演算法來將系統部分做最佳化。
  我們已經成功的將一個三階ㄧ位元切換電容型式三角積分類比數位轉換器設計自動化了,其中也應用了模擬退火演算法做系統的最佳化。設計時間大約可縮短在ㄧ天之內完成。並且最後模擬的SNDR可達到87dB,只比Matlab最佳化後少大約6dB,也就是一個位元,算是相當接近的結果。並且根據我們的實驗,只要sigma delta modulator的系統模型能夠在Matlab Simulink中架構出來,就可以使用模擬退火演算法做最佳化。論文最後再和一個經由我們人工設計的低電壓低功率三角積分器做比較。
  Sigma Delta Modulator Design Automation from system to circuit is presented in this paper. The sigma delta modulator design flow can be separated into the system and circuit level design. It often adopts Matlab Simulink for the system level design and utilizes circuit simulator like Hspice or Spectre for the circuit level design. We propose a methodology which is realized by a script language PERL to control and link all these simulation tools. For the purpose of the automation, we also applied simulated annealing algorithm to optimize the system parameters in the script.
  We have successfully implemented this automation flow for the switched-cap third-order feedback single loop single bit with the simulated annealing algorithm. The final SNDR of the automatically designed SDM ADC shows up to 87dB. Besides, this methodology can be applied to any architecture of the sigma delta modulators only if the system is modeled well in Matlab Simulink. Finally we compare with the results of a man designed low power low voltage SDM and the automation designed.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 自動化簡介 1
1.1 研究之背景 1
1.2研究之理由 3
1.3研究之目標 5
第二章 Sigma Delta Modulator 理論介紹 7
2.1導論 7
2.2 Nyquist Rate 取樣定理 7
2.3 Quantization 量化 8
2.4 Oversampling 超取樣 9
2.5 Noise shaping 雜訊移頻 11
2.5.1 二階sigma delta modulator 13
2.5.2 Multi bit sigma delta modulator 14
2.5.3 Feedforward sigma delta modulator 15
2.5.4 MASH 架構 16
2.5.5 Interpolative 架構 17
第三章 Sigma Delta Modulator 系統自動化
使用Simulated Algorithm 18
3.1自動化設計流程 18
3.2 為何選擇Sigma Delta Modulator? 19
3.3 最佳化SDM使用Simulated Annealing Algorithm 23
3.3.1 Simulated Annealing Algorithm簡介 23
3.3.2 Simulated Annealing Algorithm應用在SDM上 24
3.3.3 穩定度探討 31
第四章 三階SDM 設計自動化 32
4.1 SDM 設計自動化 32
4.2 系統設計自動化 33
4.2.1 Model OTA非理想效應 34
4.2.2 Model 取樣電容非理想效應 37
4.3 系統自動化結果 37
4.4 電路設計自動化 41
4.5 PERL自動化連結 45
4.5.1 PERL Script 47
第五章 自動化設計結果分析 48
5.1 自動化設計結果 48
5.2 以人工設計SDM流程及模擬設計結果 56
5.2.1 低電壓低功率SDM簡介 56
5.2.2 研究動機 57
5.2.3 架構及模擬 58
5.2.3.1 架構簡介 58
5.2.3.2 SDM系統模擬 60
5.2.4 電路設計及模擬 65
5.2.4.1 電路設計考量 65
5.2.4.1.1 OTA 設計和模擬結果 66
5.2.4.1.2 Clock generator 設計和模擬結果 73
5.2.4.1.3 Voltage boosting circuit 設計和模擬結果 75
5.2.4.1.4 One-bit comparator 設計和模擬結果 78
5.2.4.1.5 其他考量 79
5.2.4.2 雜訊模擬 80
5.2.4.3 SDM模擬結果 84
5.2.4.4 SDM模擬結果總結 90
5.2.4.5 SDM Layout圖和電子顯微鏡下的圖 91
5.2.5 量測考量 92
5.2.6 量測結果 93
5.2.6.1 預計規格與實測結果 96
5.3 比較自動化設計和人工調整的SDM 97
第六章 結論及未來展望 98
參考文獻 ..100
附錄
A多種架構的SA最佳化結果 104
[1] http://www.cadence.com/products/custom_ic/others/index.aspx
[2] Krasnicki, M.; Phelps, R.; Rutenbar, R.A.; Carley, L.R.,”MAELSTROM: efficient simulation-based synthesis for custom analog cells,” Design Automation Conference, pp. 945 – 950, June 1999.
[3] M. Hershenson, S. Boyd, and T.H. Lee, “GPCAD: A tool for CMOS op-amp synthesis,” IEEE/ACM Int Conf CAD, Beijing, China, 1998, pp296–303.
[4] G. A. S. Machado, N. C. Battersby, and C. Tomazou, “On the Development of Analogue Sampled-Data Signal Processing,” Analog Integrated Circuits and Signal Processing, 1996.
[5] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[6] Ki Young Nam; Sang-Min Lee; Su, D.K.; Wooley, B.A., “A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp 515-518, Oct. 2004.
[7] L. R. Carley, “A Noise-Shaping Coder Topology for 15+ bit Converters”, IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 267-273, Apr. 1989.
[8] P. Ferguson, Jr., et al., “An 18b 20kHz Dual Sigma-Delta A/D Converter,” Int. Solid-State Circuits Conf., Feb. 1991.
[9] F. de Jager , “Delta modulation, a method of PCM transmission using the 1-unit code,” Philips Res. Rep., Vol. 7, pp. 442-466, 1952.
[10] KiYoung Nam; Sang-Min Lee; Su, D.K.; Wooley, B.A. “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE Journal of Solid-State Circuits, Vol. 40, pp. 1855-1864, Sept.2005.
[11] Ho, C.Y.-F.; Ling, B.W.-K.; Reiss, J.D.; Liu, Y.-Q.; Teo, K.-L.; “Design of Interpolative Sigma Delta Modulators Via Semi-Infinite Programming,” IEEE Transactions on Signal Processing, Vol 54, pp. 4047-4051, Oct 2006.
[12] Yavari, M., Shoaei, O., “High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications,” IEEE International Symposium on Circuits and Systems (ISCAS), Vol 6, pp. 5593-5596, May 2005.
[13] R. Schreier, Delta-Sigma Modulators Toolbox Version 6.0, Analog Devices Inc., Norwood, MA, Jan. 1, 2003.
[14] Malcovati, P.; Brigati, S.; Francesconi, F.; Maloberti, F.; Cusinato, P.; Baschirotto, A., “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol 50, pp. 352-364, Mar 2003.
[15] Nowrouzian, B.; Pulido-Salcedo, J.; Wang, P.S., “A two-stage genetic algorithm for the design and optimization of resonator/integrator based sigma-delta A/D and D/A converters,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4265-4268, May 2006.
[16] S. Kirkpatrick, S. D. Gelatt Jr., and M. P. Vecchi, “Optimization by simulated annealing,”Science, Vol.220, pp.671-680, 1983.
[17] Tai-Haur Kuo, Kuan-Dar Chen, and Jhy-Rong Chen, “Automatic Coefficients Design for High-Order Sigma-Delta Modulators,” IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, vol. 6, pp. 6-15, Jan 1999.
[18] Hwi-Ming Wang and Tai-Haur Kuo, “An Automatic Coefficient Design Methodology for High-Order Bandpass Sigma-Delta Modulator With Single-Stage Structure,” IEEE Transactions on Circuits and Systems II, Vol. 53, pp. 580-584, July 2006.
[19] Libin Yao; Steyaert, M.; Sansen, W., “A 1-V, 1-MS/s, 88-dB sigma-delta modulator in 0.13-/spl mu/m digital CMOS technology,” IEEE VLSI Circuits Digest of Technical Papers, 16-18, pp. 180-183, June 2005.
[20] Boser, B.E.; Wooley, B.A., “The design of sigma-delta modulation analog-to-digital converters,” IEEE Journal of Solid-State Circuits, Vol 23, pp. 1298-1308, Dec. 1988.
[21] Fornasari, A.; Malcovati, P.; Maloberti, F., “Improved modeling of sigma-delta modulator non-idealities in Simulink,” IEEE International Symposium on Circuits and Systems (ISCAS), Vol 6, pp. 5982-5985. May 2005.
[22] G. Temes, “Finite amplifier gain and bandwidth effects in switched-capacitor filters,” IEEE Journal of Solid-State Circuits, vol. 15, pp. 358–361, June 1980.
[23] S. R. Norsworthy, R. Schreier, and G. C. Temes, “Delta-sigma data converters,” in Theory, Design and Simulation. Piscataway, NJ: IEEE Press, 1997.
[24] R. del Rio, F. Perez-Verdu, F.M. de la Rosa, A. Rodriguez-Vazquez, CMOS cascade sigma delta modulators for sensors and telecom: error analysis and practical design. Springer 2006.
[25] S. Rabii, and B. A. Wooley, “A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-.um CMOS,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, June 1997.
[26] Yavari, M.; Shoaei, O.; Afzali-Kusha, A., “A very low-voltage, low-power and high resolution sigma-delta modulator for digital audio in 0.25-/spl mu/m CMOS,” Proceedings of International Symposium on Circuits and Systems (ISCAS), Vol 1, pp. 1045-1048, May 2003.
[27] Sunyoung Kim; Jae-Youl Lee; Seong-Jun Song; Namjun Cho; Hoi-Jun Yoo, “An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip,” IEEE Journal of Solid-State Circuits, Vol 41, pp. 876-882, April. 2006.
[28] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “Optimal parameters for Delta-Sigma modulator topologies,” IEEE Trans. Circuits Syst., vol. 45, pp. 1232–1241, Sept. 1998.
[29] Manolis Terrovitis and Ken Kundert, “Device Noise Simulation of ΔΣ Modulators,” In www.designers-guide.org/Analysis.
[30] Richard Schreier,“Delta Sigma Toolbox,” www.mathworks.com/matlabcentral/fileexchange.
[31] Piero Malcovati, “SD Toolbox 2,” www.mathworks.com/matlabcentral/fileexchange.
[32] C. C. Enz and G. C. Temes. “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, Vol. 84, No. 11, pp. 1584-1614, November 1996.
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