臺灣博碩士論文加值系統

近年來，電子產品不僅要追求高速、高效能，必須兼備低耗電與低成本。現今全球各大半導體廠面對元件持續的微縮，除了製程上可行性限制外，開發出一個滿足高性能與可擴展性的目標相當重要。依據目前半導體產業的製程技術，2015ITRS2.0提出符合未來趨勢的新應用，主要焦點為使用Ge與III-V材料取代傳統的矽，主要原因為Ge與III-V材料具有較高的遷移率。並提出結合3D堆疊元件與低功耗元件將會是微縮的第三世代趨勢"3D Power Scaling"。
本篇論文開發出垂直堆疊結構奈米薄片電晶體，能應用在未來三維堆疊積體電路中，來提升電晶體密度來延續Moore’s law，具半導體產業應用價值，此篇論文中包含元件製程、基礎元件電特性分析、模擬物性分析。在元件結構上分為三種，第一種是堆疊結構的鰭式電晶體第二種是堆疊結構的閘極環繞電晶體，第三種是堆疊式P型通道矽鍺量子井電晶體，我們都利用氧化薄化的方式對多晶矽通道進行薄化，形成較薄主動層，氧化薄化可使通道多晶晶粒大小減小以減少晶界使漏電下降。
在基礎元件特性分析中，第一部份我們比較了堆疊鰭式電晶體的奈米通道結構比一般平板結構有較好的電特性，再進一步比較堆疊鰭式電晶體與堆疊結構的閘極環繞電晶體，堆疊結構的閘極環繞電晶體擁有更良好的電特性包含次臨界擺幅(S.S.)與較低的關閉電流( Off Current)。第二部分將探討隨著元件尺寸變寬對堆疊結構的電性影響。另外模擬物性分析中，我們使用Sentaurus TCAD模擬實體實驗的結構，驗證模擬結果與實驗數據相符。
在我們的研究中提出垂直堆疊結構奈米薄片電晶體具有良好的電特性，利用簡易製程達到所要求的元件特性，並應用在未來三維堆疊結構上。

In recreant years, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The Semiconductor ICs manufacturing companies still follow Moore's law to scaling. In addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Information processing technology is driving the semiconductor into a broadening spectrum of new applications according to 2015 ITRS 2.0 report. A significant part of the research to further improve device performance is presently concentrated on III-V materials and Ge. These materials promise higher mobility than Si devices. The combination of 3D device architecture and low power device will usher the Era of Scaling, identified in short as “3D Power Scaling”.
In order to increase transistor density for continuing Moore’s law, we implement the stacked nanosheert (NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. There are three kinds device structure. The first one is stacked Fin-FET, The second is stacked Gate all around VM-FET, The third is p-Channel Silicon/Germanium Quantum Well Multi-Gate Field-Effect-Transistor, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked Fin-FET and conventional stacked planar Fin-FET. The stacked Fin-FET exhibits the better performance. After that comparison of stacked Fin-FET and stacked GAA-FET. The stacked GAA-FET achieves lowing subthreshold swing (S.S.) and Off current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics.
In our proposed the stacked NS VM-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.

中文摘要.......................................................................................................................................i
Abstract.......................................................................................................................................iii
Acknowledge ..............................................................................................................................v
Contents......................................................................................................................................vi
Table Captions vii
Figure Captions viii
Introduction............................................................................................................................- 1 -
1-1 Challenge of Scaling Down the Transistor - 1 -
1-2 Introduction of multiple-gate device - 2 -
1-3 High mobility material - 6 -
1-4 Motivation - 7 -
1-5 Organization of This Dissertation - 11 -
Chapter 2...............................................................................................................................- 12 -
Stacked IM nanosheet pFin-FET - 12 -
2-1 Device Fabrication Process: - 12 -
2-2 Images Analysis - 15 -
2-2-1 SEM image of the device structure - 15 -
2-2-2 TEM image of the device structure - 17 -
Chapter 3...............................................................................................................................- 28 -
Stacked GAA IM pNS-FET - 28 -
3-1 Device Fabrication Process: - 28 -
3-2 Images Analysis - 31 -
3-2-1 SEM image of the device structure - 31 -
3-2-2 TEM image of the device structure - 32 -
3-5Device Simulation - 41 -
Device Structure and Parameters - 41 -
Chapter 4...............................................................................................................................- 47 -
Stacked QW IM pFin-FET - 47 -
4-1 Device Fabrication Process: - 47 -
4-2 Images Analysis - 50 -
4-2-1 SEM image of the device structure - 50 -
4-2-2 TEM image of the device structure - 51 -
4-3 Device Electrical Analysis - 52 -
4-4 Device Simulation - 53 -
Device Structure and Parameters - 53 -
Chapter 5...............................................................................................................................- 56 -
Conclusion.............................................................................................................................- 56 -
Reference...............................................................................................................................- 57 -

Chapter 1
[1-1] 2015 International Technology Roadmap for Semiconductors 2.0：http://www.itrs2.net/
[1-2] J.-P. Colinge, FinFETs and other multi-gate transistors vol. 73: Springer, 2008.
[1-3] J.-P. Colinge,“Multiple-gate SOI MOSFETs”,Solid-State Electron. vol. 48, pp. 897-905, 2004.
[1-4] J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani,“Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell”, IEEE Electron Device Lett., vol. 29, no. 5, pp. 518-521, May 2008.
[1-5] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, J. Y. Chin, P. H. Yeh, L. W. Feng, S. M. Sze, C. Y. Chang, and C. H. Lien, “Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics”, Appl. Phys. Lett., vol. 91, pp. 193103, Nov. 2007.
[1-6] S. Friedrich,“ High-mobility Si and Ge structures”, Semicond. Sci. Technol., vol. 12, pp. 1515-1549, 1997.
[1-7] S.-H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J.-Y. Ahn, H. Choi, et al., “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, in Reliability Physics Symposium (IRPS), 2011 IEEE International, 2011, pp. 2E. 4.1-2E. 4.4.
[1-8] B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, et al., “Vertically integrated multiple nanowire field effect transistor”, Nano letters, vol. 15, pp. 8056-8061, 2015.
[1-9] S.-D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M.-H. Na, “Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond”, in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, 2015, pp. 1-3.

Chapter 2
[2-1] Park, J.K., Kim, S.Y., Lee,K. H.,Pyi, S. H., Lee, S. H., & Cho, B. J.“Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications” , VLSI Technology(VLSI-Technology):Digest of Technical Papers, pp.1-2.2014.
[2-2] Yeh, M.S .,Wu, Y. C., Wu, M. H., Jhan, Y. R., Chung, M. H., Hung, M. F. “High performance ultra-thin body(2.4nm) poly-Si junctionless thin film transistors with a trench structure” , IEDM,pp.26-6.2014.
[2-3] Y. C. Cheng, H. B. Chen, M. H. Han, N. H. Lu, J. J. Su, C. S. Shao, Y. C. Wu, “Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor” , Nanoscale Res Lett, vol.9 , pp.392-392, 2014.

Chapter 3
[3-1] Kim, B., Lim, S. H., Kim, D. W., Nakanishi, T., Yang, S., Ahn, J. Y., Hwang, K., Kang, C.J.“Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash” , In Reliability Physics Symposium(IRPS), pp.126-129
[3-2] D. Jang, D. Yakimets, G. Eneman, P. Schuddinck, M. G. Bardon, P. Raghavan, et al., “Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node”, IEEE Trans. Electron Devices, vol. 64, pp. 2707-2713, 2017.
[3-3] TCAD Sentaurus Device, Ver.G-2012.06, Synopsys 2012.
 

Chapter 5
[5-1] Park, J.K., Kim, S.Y., Lee,K. H.,Pyi, S. H., Lee, S. H., & Cho, B. J.“Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications”, VLSI Technology(VLSI-Technology):Digest of Technical Papers, pp.1-2.2014.
[5-2] Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm)”, Electron Devices Meeting (IEDM), 2012 IEEE International, 2012.