臺灣博碩士論文加值系統

摘要

本篇論文主要研究利用帶對帶穿隧(band-to-band tunneling)機制的穿隧式場效電晶體(TFET)。TFET具有相當大潛力可作為下一代低功耗與低電壓操作的電晶體選項之一，由於TFET和MOSFET的操作機制並不相同，能夠避免許多可靠性問題和短通道效應。TFET具有小於60mV/dec.的次臨界擺幅和一個非常小的的漏電流，這些特性有利於操作偏壓的微縮與降低操作功耗的優點，可應用在低功耗元件。但是TFET仍有一些問題需要克服，如低操作電壓值、相對大的閘極-汲極電容。
為了進一步改善TFET操作特性，本篇論文提出一個新型TFET結構，其具有直立式源極-通道重疊區域，故稱作直立式通道穿隧式場效電晶體(vertical channel TFET, VC-TFET)。我們將此VC-TFET建構在鍺與矽鍺材料上，並利用TCAD模擬軟體做進一步的參數調變和進一步的研究討論。透過調變VC-TFET中的重要元件參數來優化元件特性，我們將可獲得高操作電流、低漏電流和較陡峭的次臨界擺幅等電特性。
在探討TFET的基礎特性和元件設計後，本篇論文還進一步探討VC-TFET的電容值和相反器特性。此外，另一個關鍵的問題即是TFET很大的閘極-汲極電容，這會使電路的操作速度變慢。我們提出的新型VC-TFET結構將可降低閘極-汲極電容並能改善電路操作速度。另外，本篇論文還提出新型的VC-TFET元件的SRAM電路架構，能夠在低操作電壓下達到較佳的SNM(static noise margin)。此新型VC-TFET SRAM架構設計比傳統CMOS SRAM還有更佳的SNM特性，因此VC-TFET有極大潛力被視為未來低電壓及低功耗應用的元件之一。

Abstract

In this thesis, tunneling field-effect-transistor (TFET) based on the mechanism of band-to-band tunneling (BTBT), has been studied extensively. TFET is considered as a potential low voltage and low power transistors in certain applications for next generation transistors. Since the operating mechanism of TFET and MOSFET are different, hence, TFET is able to avoid many of the reliability and short channel issues. TFFT has the capability of achieving the sub-threshold slope of less than 60 mV/decade and small leakage current. These characteristics allow the voltage scaling and also reduce the power consumption for low power application. TFET still has some issues such as low on-state drive current value and larger gate-to-drain capacitance.
To further improve the TFET performance, a novel TFET device with vertical source-channel overlap region is proposed. Ge and SiGe materials are used for the structural modelling of VC-TFET. Various design parameters of vertical channel Tunnel FET (VC-TFET) are discussed and studied in detail by using the TCAD simulation. By modulating the important device parameters to optimize the device, the electrical characteristics with improved ON-state drive current, reduced OFF-state leakage current and steeper sub-threshold swing have been achieved.
After introducing the fundamental characteristics and device design concept of TFET device, the capacitance characteristics and inverter characteristics of the VC-TFET are also discussed in this work. Another critical issue is large gate-to-drain capacitance, Cgd in TFET, which can degrade the circuit delay. The proposed vertical channel TFET device design can reduce the Cgd value which result in lower circuit delay. Novel SRAM circuit topologies based on the proposed VC-TFET device are also proposed and discussed extensively. Better static noise margin can be achieved for lower VDD value. The proposed SRAM topologies based on VC-TFET device design give better noise-margin as compared to the conventional CMOS SRAM. These results show that the proposed VC-TFET is a potential device design for low voltage and low power applications.

Chinese Abstract …………………………………………………… i
English Abstract …………………………………………………… iii
Acknowledgement …………………………………………………… v
Table of Contents …………………………………………………… vi
Table Captions …………………………………………………… xi
Figure Captions …………………………………………………… x
Chapter 1 Introduction ………………………………….... 1
1.1 Background …………………………………….. 1
1.2 Motivation …………………………………….. 3
1.3 Thesis Organization …………………………… 5
Chapter 2 Simulation Setup and Physical Model ……… 7
2.1 Introduction …………………………………… 7
2.2 Simulation Setup ……………………………… 8
2.1.1 Sentaurus Structure Editor …………………… 9
2.1.2 Sentaurus Device ……………………………... 9
2.2 Tunneling Model……………………………… 11
Chapter 3 The Characteristics of Different Tunneling FET Device Structures …………………………… 15
3.1 Introduction …………………………………. 15
3.2 Simulation Structure and Characteristic of Double Drain U-Shaped TFET ………………………. 16
3.3 Results and Discussion ……………………… 17
3.3.1 Different Doping Concentration Effect ………. 17
3.3.2 Different Intrinsic Thickness Effect …………….. 18
3.4 Simulation Structure and Characteristic of Single Drain U-Shaped TFET …………………………. 19
3.5 Results and Discussion ………………………... 20
3.5.1 Different Doping Concentration Effect ………. 20
3.5.2 Different Intrinsic Length Effect …………….. 21
3.5.3 Distributions of Electric Field and Tunneling Rate 22
3.6 Optimization of Vertical Channel TFET………. 23
3.7 Device Design Concept ………………………... 24
3.7.1 Structural Modeling…...………………………... 24
3.7.2 Band Modeling ………...……………………….. 25
3.8 Simulation Structure and Physical Model…….. 26
3.9 Results and Discussion ………………………... 27
3.9.1 Different Doping Concentration Effect ………. 28
3.9.2 Different Channel Length Effect ……………… 29
3.9.3 Different Intrinsic Length Effect …………….. 31
3.9.4 Electric Field and Tunneling Rate Distribution … 31
3.10 Summary …………………………...……….….. 32
Chapter 4 The Capacitance Analysis of Vertical Channel TFET and Circuit Performance ……………. 76
4.1 Introduction ………………………………….... 76
4.2 Capacitance Analysis of Vertical Channel TFET …………………………………………... 78
4.3 Inverter Analysis of Vertical Channel TFET ………………………………………….. 80
4.4 SRAM using Vertical Channel TFET ………….. 81
4.4.1 Conventional 6T SRAM …….………………….. 82
4.4.2 Novel 8T SRAM Cell (I) …….…………………. 84
4.4.3 Novel 8T SRAM Cell (II) …….…………...……. 85
4.4.2 Analysis of SNM ……………..………………… 86
Chapter 5 Summary and Conclusion …………………...... 102
References …………………………………...…………......... 105

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