臺灣博碩士論文加值系統

本研究以Microsoft Visual Studio(MVS) 2010軟體實現視窗化FIR濾波器整合式設計自動化系統(Integrated FIR IP/Chip Design Automation，IFICDA)，提供使用者簡單的GUI設計介面設定濾波器參數，系統自動合成該濾波器之優化RTL Code，自動合成邏輯閘電路，進而電路模擬驗證，以及最後自動化晶片佈局設計。該系統以數種FIR數位濾波器晶片設計實例進行驗證，其晶片效能良好且設計程序順暢簡潔。
[9] [10]等人的CSE(Canonic Signed Digit)演算法與[11][12]布斯(Booth)演算法在FIR數位濾波器設計化簡上都有良好的化簡成效，但研究中發現[10]在群組化簡的優勢中同時也出現了過償化簡的疑慮，足以影響其群組化簡的成效。在IFICDA中提出一種新型貪婪式演算法，首先將濾波器的係數乘積項分別表示成Booth、CSD以及使用前兩者結合的混合式(Mixed Mode)表示式，接著分別進行無償反覆式HCSE(Horizontal Common Subexpression Elimination)化簡、有益的(Effective) HCSE化簡，分別來解決浪費無償及使用過償化簡的缺陷。在無償反覆式HCSE化簡中定義SG(Select Gain)值做為群組有效選用的準則與依據，讓化簡群組的選用標準化，而不會在群組化簡過程中錯失效率較佳的群組。在有益的HCSE化簡中也定義有益之衡量準則，避免使用過償化簡。最後，進行最佳解選擇來選用三種表示法中效能優化最好的一種，作為FIR數位濾波器的IP產生，輸出性能較佳的RTL Code。
本研究在IFICDA中結合了晶片設計領域，設計了一套Cell Based晶片設計自動化的CDA流程。CDA流程中產生一ACD.scr檔，該檔使用本校電子系”晶片實現與應用”研究室成果”OitCellLibrary”，結合Design Compiler軟體的邏輯合成功能，將前述之RTL Code合成邏輯閘階層的Gate Level檔，並用Encounter軟體對Gate Level檔進行APR(Auto Place & Route)程序，產生FIR數位濾波器晶片設計。系統也結合Hspice模擬功能，提供對Gate Level檔進行電路模擬驗証。
本文中以49Taps、20位元字組(5Integer+15Float)之各類FIR數位濾波器規格，實際應用在IFICDA 系統上進行自動化設計驗證。該新型貪婪式演算法化簡效率可達到68.0%以上，平均每顆晶片設計的生成時間也在短短的10分鐘之內。這證實IFICDA軟體使用新型貪婪式演算法改善FIR數位濾波器效能，產生RTL Code結合CDA流程快速跑通晶片設計流程而產生晶片雛型，大大的縮短FIR數位濾波器晶片設計的開發時程。

In this study, we used the Microsoft Visual Studio(MVS) software to achieve Integrated FIR IP/Chip Design Automation(IFICDA) system, provide user a simple GUI interface to set the filter parameters, automatically synthesize the filters of optimize RTL Code, automatic synthesis of logic gates and thus the circuit simulations, and automated chip layout design in final. Validate examples of the system for several FIR digital filter chip design, and the chip performs well and the design process is smooth and simple.
CSE (Canonic Signed the Digit) algorithm [9-10] and Booth algorithms have well effectively simplification in the simplification of FIR digital filter design. However, the study found the advantages of simplification group but also concerns of overhead in simplification. That affects the effectiveness of the simplification group. We proposed a new greedy algorithm in IFICDA, first the product term of the filter coefficients are represented as the Booth and CSD as well as Mix expression using a combination of both, and then were the free-paid iterative HCSE (Horizontal Common Subexpression Elimination) simplification and effective HCSE simplification. Respectively, that solves defects of the ungrouped free-paid group and award use of over-paid grouped simplification. The definition of the SG (Select Gain) values as a criterion of group selecting in free-paid iterative HCSE simplification algorithm, this standardization of selecting of simplification group will not miss the group of better efficiency in the process of group simplification. We also defined useful measurement criteria in effective HCSE simplification, and avoid the award use of over-paid simplification. Finally, we select optimal solution from these simplifications of three represents, to generate the IP of the FIR digital filter, to export the better performance of RTL Code.
In this study, chip layout design included in IFICDA, proposed a chip design automation of CDA process based on Cell-based. CDA process generates an “ACD.scr” file automatically. In IFICDA, the ACD file uses “OitCellLibrary” of OIT Lab results of chip and application, launches Design Compiler to synthesis the logic gates using aforementioned RTL code, and then runs APR (Auto Place & Route) program by Encounter to produce the FIR digital filter chip layout design. The system is also combined with Hspice simulation, provides circuit simulation and verification of the Gate Level file.
A few various types of FIR digital filter specifications of 49taps, 20-bit word (5 integer bits + 15 float bits), have been applied in the IFICDA system for automated design verification. The efficiency of the greedy algorithm can reach more than 68.0%, and the average generation time for each chip design is also in 10 minutes. These application practical confirm the greedy algorithm improving the FIR digital filter design performance in IFICDA, from efficient RTL Code generation to quickly run through the chip design process, greatly shorten the development time of FIR digital filter chip design.

致謝
摘要
Abstract
目錄
表目錄
圖目錄
第一章 緒論
第二章 數位濾波器技術探討
2-1 FIR濾波器基礎架構
2-2 FIR濾波器設計探討
2-3 CSE演算法
2-4 SRRC設計範例應用CSE演算法
第三章 新型貪婪式演算法
3-1新型貪婪式演算法流程
3-2混合式表示法
3-3 無償反覆式HCSE化簡
3-4 有益的(Effective)HCSE簡化
3-5 最佳解尋找
3-6 SRRC設計實例
3-7 更多FIR設計實例驗證與效能比較
第四章 整合式FIR自動化晶片設計
4-1 FIR自動化晶片流程
4-2 Specific Definition
4-3 Automatic Chip Design (ACD)
第五章 研究數據
5-1 FIR濾波器自動化晶片設計成果
第六章 結論與未來展望
參考文獻

[1] Robert J. Schilling and Sandra L. Harris, “數位訊號處理”, Thomson, 2006。
[2] M. Mehendale, S. D. Sherlekar, and G. Venkatesh, “Synthesis of multiplierless FIR filters with minimum number of additions,” in Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design”, CA: IEEE Computer Society Press, Los Alamitos, 1995, pp. 668-671.
[3] T. Kean, B. New, and B. Slous. “A fast constant coefficient multiplier for the XC6200,” Lecture Notes in Computer Science, 1996。
[4] A. Booth, “A signed binary multiplication technique,” Q. J. Mech, Appl. Math, vol. 4, pp.236-240, 1951。
[5] 廖浩凱，”應用於三角積分類比/數位和數位/類比轉換器之可程式化降頻和升頻濾波器”，南台科技大學電子工程系，碩士論文，2002。
[6] 蕭如宣，李進華，“最佳化SRRC濾波器設計”，亞東學報，P23~P32，2006。
[7] I. Richard and Hartley, "Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers," IEEE Transaction on Circuits and Systems, Vol. 43, No. 10, Oct. 1996.
[8] 許水紋，”使用CSD表示法之運算共享可程式FIR濾波器設計”，國立清華大學產業研發碩士積體電路設計專班，碩士論文，2007。
[9] A.P.Vinod and E.M-K.Lai, "Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters," IEEE International Symposium on Circuits and Systems (ISCAS) on Japan, May 2005, pp. 496-499.
[10] Vijay, S. , Vinod, A.P. and Lai, E.M.-K., “A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters”, IEEE International Symposium on Circuits and Systems (ISCAS) on New Orleans, LA, 2007, pp. 3451 - 3454.
[11] 蕭如宣、曾智宏，”SRRC IP 產生器設計與實作”，第六屆智慧生活科技研討會，台中，2011，頁796-801。
[12] Rajendra Katti, “A Modified Booth Algorithm for High Radix Fixed-point Multiplication,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL 2, NO 4, pp.522-524, Dec. l994。
[13] Keshab K. Parhi, ”Digital Signal Process for Multimedia Systems”, March 11, 1999 by CRC Press.
[14] P. E. Madrid, B. Millar, and E. E. Swartzlander, “Modified Booth algorithm for high radix fixed-point multiplication,” IEEE Trans, VLSI Syst. Vol. 1, No. 2, pp. 164 -167, June 1993。
[15] 薛玉旺，“平方根升餘弦濾波器的FPGA實現”，北京郵電大學論文，2007。
[16] “DesignCompiler”，http://wenku.baidu.com/view/cd5cf7eb998fcc22bc d10d7a.html。
[17] “Cadence Encounter”， https://vlsiwiki.soe.ucsc.edu/index.php/Caden ce_Encounter。
[18] “SoC Encounter”， http://www.docin.com/p-55376178.html
[19] “CIC 教育訓練課程”，http://www.cic.org.tw/cic_v13/reg_service/con tent/regmain.jsp?PROG_ID=regworkm44&ITEM=1&groupid=10741&G_KIND=EDU
[20] 陳昱達，“無量測器內置永磁同步馬達向量控制晶片設計”， 國立臺灣科技大學電機工程系，碩士論文，2009。
[21] 蕭如宣，“VHDL數位電路設計”，儒林，2002。
[22] 蕭如宣，“ SOPC系統設計”，儒林，2003。
[23] 廖文良，“Visual C# 2005檔案IO與資料存取祕訣”，碁峯，2006。
[24] 蔡煥麟，“軟體工程與Microsoft Visual Studio Team System”，碁峰資訊，2006。