臺灣博碩士論文加值系統

本研究藉由CMOS製程平台的多層膜堆疊特色，以垂直整合電容式濕度感測器以及阻值式溫度感測器，達到提高面積使用效率的整合型溫濕度環境感測器。在電容式濕度感測元件方面，提出柵欄狀的出平面平行板電容作為濕度感測元件的主要結構，並選用具有感測水氣功能且相容於CMOS標準製程的聚酰亞氨作為感濕材料。在阻值式溫度感測元件方面，主要是垂直整合於濕度感測器的正上方，可直接性地藉由量測阻值得知環境中的溫度。此外，本文設計的感測元件是使用TSMC 0.18μm 1P6M CMOS標準製程平台，並搭配後製程規劃完成元件。
本研究實驗量測結果顯示，柵欄狀的平行電容板結構搭配使用PI材料作為感濕膜層的濕度感測器，其感測靈敏度與反應時間兩項重要指標的量測結果分別為0.051%/%RH和16s；此外垂直整合的阻值式溫度感測器是採用蛇狀繞折式的M5層組成，其靈敏度為0.28%/℃。

This study demonstrates the vertically integrated environment sensor with a capacitive relative humidity sensor (RH sensor) and a resistive temperature detector (RTD) using the TSMC 0.18μm 1P6M CMOS process and simple in-house post-CMOS processes.
Features of this study are: (1) multiple sensing unit could be integrated and achieved in one chip; (2) fast response humidity sensor are realized based on capacitive sensing principle; (3) simple post-CMOS processes using metal wet etching, reactive ion etching, pneumatic dispensing of polyimide (PI), curing process, and wire bonding. The main measurement results indicate the RH sensor with sensitivity of 0.051%/%RH and response time of 16s; thus, the sensitivity of RTD is 0.28%/℃.

摘要 I
Abstract II
誌謝 III
目錄 V
圖目錄 VII
表目錄 XI
第1章 緒論 1
1-1 前言 1
1-2 濕度感測器發展現況 3
1-3 文獻回顧 4
1-3-1 相對濕度感測機制分類 6
1-3-2 電容式濕度感測材料類別 10
1-3-3 CMOS-MEMS後製程 13
1-4 研究動機與目標 15
第2章 元件設計與分析 28
2-1 TSMC 0.18µm 1P6M CMOS製程平台 28
2-2 電容式濕度感測原理 29
2-2-1 電容式濕度計靈敏度與初始電容 29
2-2-2 濕度計反應時間 33
2-2-3 電阻式溫度感測原理 35
2-3 元件設計與模擬 36
2-3-1 元件結構設計 36
2-3-2 元件性能模擬 37
第3章 光罩佈局與後製程結果 46
3-1 溫濕度結構佈局 46
3-2 CMOS晶片後製程 47
3-3 後製程結果 50
第4章 量測結果與討論 61
4-1 結構表面形貌 61
4-2 濕度感測元件量測 62
4-3 元件反應時間量測 64
4-4 溫度感測元件量測 65
4-5 討論 66
第5章 結論與未來工作 80
5-1 結論 80
5-2 未來工作 81
參考資料 85

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