臺灣博碩士論文加值系統

隨著製程越來越先進，和系統單晶片的時脈操作越來越快，變異對於系統的效能影響也就越大，時脈抖動是會影響系統效能的一個變異，但大部分的晶片測試中，很難針對時脈抖動來量測。過去時脈抖動多由外部儀器量測，但由於系統的操作頻率不斷提高，欲達到較高量測效能，將會相對的提高外部儀器成本，再加上外部儀器的探針會引入雜訊，影響量測結果。為了更有效的量測時脈的抖動，因此使用內建時脈抖動量測電路較外部量測適用於量測時脈抖動。
然而，在量測抖動的過程中如果發生變異，將會影響量測抖動的結果，進而提供給使用者錯誤的抖動資訊，所以本論文提出適用於DDR4-3200之高解析度、低抖動量量測誤差、抗變異時脈抖動感測器設計[1]。相較於傳統設計，我們新提出了即時且自動校準解析度電路，在量測DDR4-3200的時脈抖動時，此電路在每次的量測模式前會進行晶片內部校準，並且校準出的解析度會判斷是否有動態的變異發生，如果有變異發生，會改變整時脈抖動感測器的解析度來達到降低量測誤差。
本論文以UMC 28nm製程實現，電路的工作電壓為0.9V。電路操作頻率依據DDR4-3200的規格1.6GHz，整體電路解析度在1ps，消耗功率約2.13mW，核心電路面積約為167um×98um，最糟量測誤差由傳統時脈抖動感測器的331%降低至-148%。

As the technology node progresses and the operating frequency of circuit and system increases, variation’s affection becomes more and more critical, and jitter effect is one of the most severe variations.
However, jitter effect is difficult to be measured and quantified in most on chip systems. In the past, jitter had to be measured via external equipment, but as the operating frequency rise, the equipment which is able to conduct high frequency jitter measurement are costly, and the probe-caused noise will affect the measurement results. To measure jitter more effective, on-chip jitter sensor is a better choice than external equipment. However, if the variation occurs during measurement phase, the results will have great chance being flaw. This paper proposed design of high resolution, low measured jitter error and variation resilient on-chip jitter sensor for DDR4-3200 [1]. Compare to conventional jitter sensors, we propose run-time automatic resolution calibration circuit. Resolution calibration will be done before every measurement phase, after calibration our jitter sensor can detect active variation occurrence and dynamically adjust resolution.
This work is done in UMC 28nm process, 0.9V operating voltage, and the operating frequency is same as DDR4-3200 circuit, 1.6GHz, with 1ps resolution, 2.13mW power consumption and approximate 167nm×98um die area, worst case measurement error improve from 331% to -148%.

誌謝辭 i
摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 緒論 1
1.1 背景簡介和動機 1
1.2 論文架構介紹 2
第二章 時脈抖動基本定義介紹與傳統時脈抖動量量測方法介紹 3
2.1 時脈抖動定義及分類 3
2.1.1 時脈抖動基本定義 3
2.1.2 週期對週期性時脈抖動 3
2.1.3 週期性時脈抖動 3
2.1.4 長期性時脈抖動 4
2.1.5 均方根抖動與峰對峰值抖動 4
2.2 傳統外接式時脈抖動量測方法介紹 5
2.3 傳統內建式時脈抖動量測感測器(OCJS)方法介紹 6
2.3.1 延遲串列式量測法 6
2.3.2 游標尺延遲線量測法 7
2.3.3 具自我取樣技巧之時脈抖動量測感測器 7
2.3.4 具時間差放大技巧之時脈抖動量測感測器 8
2.3.5 傳統式時脈抖動量測感測器運作原理 9
第三章 內建式時脈抖動量感測器量測誤差的成因與分析 11
3.1 內建式時脈抖動感測器量測誤差的原因 11
3.2 分析電壓與溫度變異對內建式時脈抖動感測器關鍵電路的影響 11
3.2.1 自我參考時脈產生電路 11
3.2.2 時間差放大器 13
3.2.3 游標尺震盪器 14
3.2.4 整體OCJS電路解析度 16
3.3 分析內建式時脈抖動量感測器之量測誤差模擬結果 17
第四章 低抖動量量測誤差且抗變異時脈抖動感測器 20
4.1 低抖動量量測誤差且抗變異時脈抖動感測器電路架構及原理介紹 20
4.1.1 低抖動量量測誤差且抗變異時脈抖動感測器架構說明 20
4.1.2 低抖動量量測誤差且抗變異時脈抖動感測器動作原理 20
4.2 子電路說明與設計考量 23
4.2.1 自我參考訊號產生電路 23
4.2.2 自動限制時間放大器輸入相位電路 25
4.2.3 時間差放大器 26
4.2.4 游標尺震盪器 27
4.2.5 即時且自動校準解析度電路與校準電路 29
第五章 電路模擬結果 31
5.1 子電路模擬結果 31
5.1.1 自我參考時脈產生電路 31
5.1.2 時間差放大器 33
5.1.3 游標尺震盪器 36
5.1.4 即時且自動校準解析度電路 37
5.2 整體電路模擬結果 41
5.2.1 環境設定為FF,0.99V,-40℃輸入抖動量62.5ps電路模擬結果 41
5.2.2 環境設定為SS,0.81V,-40℃輸入抖動量62.5ps電路模擬結果 42
5.2.3 總結 43
第六章 結論及未來研究 44
6.1 結論 44
6.2 未來研究 44
參考文獻 45

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