臺灣博碩士論文加值系統

本論文提出一個利用40 奈米互補式金屬氧化半導體製程之寬頻有線通訊發送測試系統，此發送系統可提供接收端測試當今25 Gb/s、28 Gb/s、及32 Gb/s不同的有線通訊傳輸規格，並提供四種不同方式的資料序列：27-1、215-1、223-1及231-1和四種誤碼注入的功能: 10-3、10-6、10-9、及0，其內部具有一組寬頻鎖相迴路(Phase-Lock Loop)以自行產生一組穩定的時脈提供給發送器觸發，最高速度可達32 Gb/s。
此發送系統由多工器、正反器、除頻器、前饋等化器及鎖相迴路所組成，由內建的鎖相迴路產生一組半速率的時脈來觸發輸出全速率的資料序列，並透過結合輸出級之前饋等化器，補償高速資料序列在通道傳遞時所造成的損失。此外，藉由內建自動相位調節器調整資料與時脈之間的相位關係，使取樣點在不同頻率下皆在最佳位置。量測時，最高量測至32 Gb/s的資料序列輸出，在前饋等化器開啟下，雙端差動擺幅為700 mV，功率消耗為755 mW。不同的資料序列、誤碼注入及前饋等化器的增加量皆可透過可程式化開發板進行控制選擇，並在位元錯誤偵測器下進行20 Gb/s ~ 32 Gb/s資料序列的比對驗證，資料序列及誤碼注入皆為正確。除了透過接合導線(Wire-bonding)的方式進行晶片的量測之外，最後此晶片並透過四方平面無引腳封裝(Quad Flat No leads)使晶片更加完整。

This thesis presents a wide-rage wireline transmitter system in 40 nm CMOS technology. It can provide the receiver for testing with different standard of wireline communication such as 25 Gb/s、28 Gb/s and 32 Gb/s. It can also generate different types of PRBS data sequence：27-1、215-1、223-1、231-1 and four types of error injection rate to data sequence：10-3, 10-6, 10-9, and 0. With a built-in wide-rage phase-locked Loop, it can regard as a clock source of the system, which can be operated up to 32 Gb/s.
This wireline transmitter system includes multiplexers, flip-flops, dividers, feed-forward equalizer and phase-locked loop. It can be triggered full-rate output data sequence by half-rate clock output from phase-locked loop integrated in the chip. Also, the channel loss can be compensated by the driver with feed-forward equalizer while transmitting data sequence. Also, the clock sample the data at the best sampling point under different frequency by the auto phase adjusted circuit. The measurement output data rate is up to 32 Gb/s and the output swing is 700mV in differential when feed-forward equalizer is ON. The whole system consumes 755mW. It can be selected different types of PRBS pattern, error injection and boosting amount of feed-forward equalizer by controlling the field programmable gate array (FPGA). The data sequence and error injection are confirmed in the operating range 20 Gb/s ~ 32 Gb/s under the bit-error-rate tester (BERT). Besides measuring the chip by bonding wire, the whole system is also packaged in QFN (Quad Flat No leads) to make the whole chip more complete.

口試委員會審定書 #
誌謝 i
ABSTRACT iii
LIST OF FIGURES vi
LIST OF TABLES ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the thesis 3
Chapter 2 Background 4
2.1 Pseudo Random Binary Sequence 4
2.1.1 Function of the Pseudo Random Binary Sequence 4
2.1.2 Principle of the Pseudo Random Binary Sequence 5
2.2 Serial-Link Transmitter Basics 6
2.2.1 Basic Transmitter Architecture 6
2.2.2 Performance metrics of Transmitter 7
2.3 Serialization and Channel Equalization in Transmitter 10
2.3.1 Serialization 10
2.3.2 Channel Equalization 13
2.4 Design Challenges for wide-range operation 18
2.5.1 Timing Constraints 18
2.5.2 Limited Bandwidth and Bandwidth extension technique 20
2.5.3 Architecture Comparison 21
Chapter 3 A 20-32 Gb/s Transmitter System for Wireline Communication Testiing in 40 nm CMOS technology 24
3.1 Architecture 24
3.2 The Digital Part and Low Speed MUX 25
3.2.1 The Digital Part 26
3.2.2 64:16 MUX 27
3.2.3 16:4 MUX 29
3.2.4 4:2 MUX 31
3.3 The 2:1 MUX with Half-Rate Feed-Forward Equalizer 32
3.2.1 Structure 32
3.2.2 Latch and Selector 33
3.2.3 Pre-Driver and Output Driver 36
3.4 Auto-Phase Adjusted Circuit 38
3.4.1 Timing Issue 38
3.4.2 Structure 40
3.4.3 Loop Behavior 41
3.4.4 Building Blocks 42
3.4.5 Simulation Result 44
3.5 Integrated with Wide-Range Phase-Locked Loop 45
Chapter 4 Measurement Result 47
4.1 Environment Setup 47
4.2 Measurement Result 49
Chapter 5 Conclusions 54
REFERENCE 55

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