臺灣博碩士論文加值系統

本篇論文設計符合直接序列極寬頻（Direct Sequence Ultra-Wide Band, DS-UWB）系統的基頻整合晶片，其中我們針對威特比解碼器提出一個低複雜度的電路架構，此電路採用比較選擇加法單元(compare-select-add unit, CSAU)與追蹤前置架構(trace forward)。首先在比較選擇加法單元中的判斷位元決定運算，我們觀察其運算間符號的變化來做簡化，僅使用一個加法運算來降低複雜度。另外在殘存管理單元(survivor management unit, SMU)使用兩組追蹤前置，藉由排列記憶體讀取順序來變更管理方式，因此將記憶體個數簡化為兩塊長度為T的單埠記憶體，達到降低使用記憶體面積之目的。
晶片模擬是使用TSMC 0.18-μm 1P6M CMOS製程，其電路核心面積為1.061 × 1.069 mm2。在1.8伏特與25 的後佈局模擬環境下，我們提出的直接序列極寬頻系統基頻晶片其工作頻率可達到141 MHz，功率消耗為86.41 mW。

A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM’s with a length of T are applied for reducing the area of memory.
The chip is implemented by TSMC standard 0.18-μm 1P6M CMOS process with core area 1.061 × 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.

誌謝 ……………………………………………………………………………….i
摘要 ………………………………………………………………………………ii
Abstract ……………………..……………………………………………………….iii
目錄 ………………………..…………………………………………………….iv
圖索引 …………………………..………………………………………………….vi
表索引 ………………………………….………………………………………….ix
第一章 緒論 1
1.1 研究背景與動機 1
1.2 各章提要 3
第二章 直接序列極寬頻系統規格與架構 4
2.1 DS-UWB實體層規格 4
2.1.1 前置序列 4
2.1.2 資料序列 6
2.1.3 混擾器 7
2.1.4 迴旋編碼器 8
2.1.5 交錯器 9
2.1.6 根餘弦濾波器 10
2.2 通道模型 13
2.3 接收機設計 17
2.3.1 訊號能量偵測 18
2.3.2 最大能量獲取 20
2.3.3 粗略通道估測 23
2.3.4 訊框起始偵測 28
2.3.5 決策回饋等化 31
第三章 威特比解碼器電路設計 43
3.1 迴旋碼編碼與解碼原理 43
3.2 威特比解碼器架構設計 44
3.2.1 分支路徑單元 45
3.2.2 比較選擇加法單元 48
3.2.3 殘存管理單元 52
第四章 系統模擬與晶片設計 61
4.1 系統整合架構 61
4.1.1 收發機資料規格與處理流程 61
4.2 接收機各階段位元決定 63
4.3 晶片設計流程 74
4.3.1 ModelSim Simulation 76
4.3.2 佈局與繞線 78
4.3.3 DRC驗證 79
4.3.4 LVS驗證 80
第五章 結論 81
參考文獻 82

[1] J. G. D. Forney, “The Viterbi algorithm,” Proc. IEEE, vol. 61, no. 3, pp. 268–278, Mar. 1973.
[2] G. Fettweis and H. Meyr, “A 100 MBit/s Viterbi decoder chip: Novel architecture and its realization,” in Proc. IEEE Int. Conf. Communications (ICC), vol. 2, pp. 463–467, Aug. 1990.
[3] P. J. Black and T. H. Meng, “A 140-Mb/s, 32-state, radix-4, Viterbi decoder,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1877–1885, Dec. 1992.
[4] C. M. Rader, “Memory management in a Viterbi decoder,” IEEE Trans. Commun., vol. 29, no. 9, pp. 1399–1401, Sep. 1981.
[5] A. J. Viterbi and J. K. Omura, Principles of Digital Communication and Coding. New York: McGraw-Hill, 1979.
[6] DS-UWB Physical Layer Submission to 802.15 Task Group 3a, IEEE, Jan. 2005.
[7] Channel Modeling Sub-committee Report Final, IEEE 802.15 Task Group 3a, Dec. 2002.
[8] Z. Tian and B. Sadler, “Weighted energy detection of ultra-wideband signals,” in Proc. IEEE Signal Processing Workshop on Advances in Wireless Communications, pp. 158-168, June 2005.
[9] A. Rabbachin, I. Oppermann, and B. Denis, "ML time-of-arrival estimation based on low complexity UWB energy detection," in Proc. IEEE Int. Conf. on Ultra-Wideband (ICUWB), pp. 598-604, Sep. 2006.
[10] Z. Tian, V. Lottici, “Low-Complexity ML Timing Acquisition for UWB Communications in Dense Multipath,” IEEE Trans. Commun., vol. 4, no. 6, pp. 3031-3038, Nov. 2005
[11] A. Kocian, I. Land and B. H. Fleury, “Joint Channel Estimation, Partial Successive Interference Cancellation, and Data Decoding for DS-CDMA Based on the SAGE Algorithm,” IEEE Trans. Commun., vol. 55, no. 6, pp. 1231-1241, Jun. 2007.
[12] Kim, B. S. Bae, J. Song, I. Kim, S. Y. Kwon, H. Kwon, “A Comparative Analysis of Optimum and Suboptimum Rake Receivers in Impulsive UWB Environment,” IEEE Trans. Vehicular Technology, vol. 55, no. 6, pp. 1797-1804, Nov. 2006
[13] I. M. Onyszchuk, K. M. Cheung, and O. Collins, “Quantization loss in convolutional decoding,” IEEE Trans. Commun., vol. 41, no. 2, pp. 261–265, Feb. 1993.
[14] A. K. Yeung and J. M. Rabaey, “A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder,” in IEEE Int. Solid-State Circuit Conf. (ISSCC) , pp. 88–89, Feb. 1995.
[15] T. Gemmeke, M. Gansen, and T. G. Noll, “Implementation of scalable power and area efficient high-throughput Viterbi decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 941–948, Jul. 2002.
[16] G. Fettweis, R. Karabed, P. H. Siegel, and H. K. Thapar, “Reduced-complexity Viterbi detector architectures for partial response signalling,” in Proc. GLOBECOM, vol. 1, Singapore, pp. 559–563, Nov. 1995.
[17] K. Page and P. M. Chau, “Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 151–155, Jan. 1998.
[18] I. Lee and J. L. Sonntag, “A new architecture for the fast Viterbi algorithm,” IEEE Trans. Commun., vol. 51, no. 10, pp. 1624–1628, Oct. 2003.
[19] C.C. Lin, Y.H. Shih, H.C. Chang, and C.Y. Lee, “Design of a power-reduction Viterbi decoder for WLAN applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 6, pp. 1148–1156, Jun. 2005.
[20] G. Feygin and P. Gulak, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoders,” IEEE Trans. Commun., vol. 41, no. 3, pp. 425–429, Mar. 1993.
[21] N.-H. Chang, Cell-based IC physical design and verification with SOC Encounter, National Chip Implementation Center, R.O.C., July 2005.