臺灣博碩士論文加值系統

本論文針對室內吵雜環境提出一即時抑制噪音源與真人語音活動偵測系統。並提出一個符合實驗室規模、8通道之即時性麥克風陣列訊號處理實驗平臺，且已實作完成。為了讓系統能適應於噪音源的變化與環境的特徵，論文中設計出一適應性空間濾波器並實做完成，其中適應性空間濾波器的啟動由真人語音活動偵測結果決定。論文中之演算法皆實現於可規劃系統晶片硬體平台上。其中真人語音偵測由Nios微處理器完成，而適應性空間濾波器由自行設計的硬體進行加速並透過Avalon Bus和Nios微處理器進行溝通。由於此適應性空間濾波器的階數為彈性化設計，可以根據不冋的環境狀況做調整，以達到較好的語音純化效果，由實驗證明，此系統能抑制干擾源的影響，有效提高訊號雜訊比。

A real-time speech purification and voice activity detection (VAD) system for noisy indoor environment is proposed in this thesis. The system contains a real-time eight channel microphone array signal processing platform. An adaptive spatial filter is also designed on the platform to provide the system with the ability of environmental characteristic and noise adaptation. All the algorithms are realized on a Nios embedded system-on-programmable-chip (SOPC) platform. The VAD algorithm is executed by the Nios processor and the adaptive filter is accelerated by a self-designed hardware, which is a customized peripheral. The communication between the Nios and processor and the customized peripheral is achieved by the Avalon Bus. Since the order of the spatial filter is flexible, the system can be adjusted for superior speech puirificaiton result. The experimental results verify that the system can suppress the effect of environmental noise and improve the SNR effectively.

摘 要 I
ABSTRACT II
誌 謝 III
目 錄 IV
表 列 VII
圖 列 VIII
第一章 緒論 1
1.1 研究動機 1
1.2 研究目標 2
1.3文獻回顧 3
1.4 論文貢獻 5
1.5 論文架構 5
第二章 適應性陣列訊號處理 6
2.1 陣列訊號處理 6
2.1.1陣列式訊號處理簡介 6
2.1.2陣列型態：均勻線性陣列（Uniform Linear Array） 8
2.1.3均勻線性陣列空間響應 9
2.1.4均勻線性陣列特性 10
2.2 語音活動偵測（VOICE ACTIVITY DETECTION，VAD） 12
2.2.1 VAD模擬 16
2.3 適應性訊號處理 18
2.3.1適應性濾波器簡介 18
2.3.2適應性濾波器處理架構 18
2.3.3 Least-Mean-Square（LMS）Algorithm 19
2.3.4 Normalize LMS Algorithm 21
2.4 適應性陣列訊號處理 22
2.4.1 適應性陣列訊號處理簡介 22
2.4.2 適應性空間濾波器：Dahl，s Algorithm 22
2.5 結合真人語音偵測與適應性陣列訊號處理 25
2.5.1結合真人語音偵測與適應性陣列訊號處理架構簡介 25
2.5.2結合真人語音偵測與適應性陣列訊號處理模擬 26
第三章 實驗平台與軟硬體設計實現 28
3.1實驗平台架構簡介 28
3.2前端麥克風陣列訊號擷取平台 29
3.2.1聲音訊號放大及濾波電路 29
3.2.2類比訊號擷取及轉換電路 31
3.2.3陣列訊號擷取電路板 32
3.3 NIOS 嵌入式SOPC發展平台 33
3.3.1 SOPC系統概述與NIOS 嵌入式SOPC發展平台簡介 33
3.3.2 Nios CPU[22] 35
3.3.3 Avalon Bus介面及使用者自訂之客製化周邊模組 37
3.3.4 DMA 控制器[22,23] 41
3.4 SOPC單晶片系統軟硬體設計 42
3.4.1 系統功能描述及系統方塊圖 42
3.4.2 系統運算量估測及軟硬體配置 44
3.4.3系統硬體架構 47
3.4.4 匯流排介面及暫存器檔案模組 51
3.4.4.1匯流排介面模組 51
3.4.4.2暫存器檔案模組 52
3.4.5 資料擷取及流程控制模組 53
3.4.5.1資料擷取模組 53
3.4.5.2流程控制模組 56
3.4.6按鈕開關偵測與濾波器階數設定模組 57
3.4.7 適應性空間濾波器模組 59
3.4.7.1八個頻道之FIR空間濾波器模組 60
3.4.7.2訊號能量計算模組 62
3.4.7.3濾波器係數更新模組 64
3.4.7.4適應性空間濾波器模組在MATLAB模擬 66
3.4.8 記憶體模組 70
3.4.8.1欲純化語音記憶體模組(欲消除雜訊記憶體模組) 71
3.4.8.2資料記憶體模組 72
3.4.8.3濾波器係數記憶體模組 73
3.4.9 Nios微處理器系統軟體架構 74
3.5實驗平台實際照片 75
第四章 實驗結果與分析 76
4.1 麥克風陣列於室內環境 76
4.1.1空間濾波器結合真人語音活動偵測與訊號雜訊比關係 77
第五章 結論 87
5.1 總結 87
5.2 未來展望 88
REFERENCE 89

[1]D. Johnson and D. Dudgeon, Array Signal Processing: Concepts and
Techniques,Prentice Hall, Englewood Cliffs, New Jersey, 1993.
[2]J. L. Flanagan﹐ L. Landgraf﹐ D. J. McLean﹐ ”Matched-filter processing
of hydrophone array”﹐J. Acousr. Soc. Am. 42,1165(A)(1967).
[3]Barry D. Van Veen and Kevin M.Buckley,”Beamforming:A Versatile Approach to Spatial Filtering,”IEEE ASSP MAGAZINE April 1988.
[4]Zoltowski, M., ”High resolution sensor array signal processing in the beamspace domain: novel techniques based on the poor resolution of Fourier beamforming,” Spectrum Estimation and Modeling, 1988., Fourth Annual ASSP Workshop on , pp. 350 –355, 1988
[5]Byung-Chul Kim; I-Tai Lu , ”High resolution broadband beamforming based on the MVDR method,” OCEANS 2000 MTS/IEEE Conference and Exhibition , Volume: 3 , pp. 1673 –1676, 2000
[6]Marciano, J.S., Jr.; Vu, T.B., ”Reduced complexity MVDR broadband beamspace beamforming under frequency invariant constraint,” Antennas and Propagation Society International Symposium, 2000. IEEE , Volume: 2 , pp. 902 –905, 2000
[7]Pillai, S. Unnikrishna, Array signal processing, 1989
[8]Ta-Sung Lee; Tsui-Tsai Lin , “Coherent interference suppression with complementally transformed adaptive beamformer,” Antennas and Propagation, IEEE Transactions on , Volume: 46 Issue: 5 , pp. 609 –617, May 1998
[9]Gollamudi, S.; Yih-Fang Huang , “Optimally combined nonlinear MMSE beamforming and interference cancellation for CDMA communications,” Personal Wireless Communications, 2000 IEEE International Conference on , pp. 474 –478, 2000
[10]黃佑霖,”應用延遲濾波器之麥克風陣列訊號處理”,交大電控碩士論文,Jun 1999
[11]陳界全,”即時聲源追蹤與空間濾波器設計”,交大電控碩士論文,Jun 2000
[12]康創閔,”應用於個人電腦環境之即時語音純化系統設計”,交大電控碩士論文,Jul 2004
[13]Ta-Sung Lee,Array Signal Processing,(class note)
[14]Javier Ramírez , José C. Segura , Carmen Benítez , Ángel de la Torre and Antonio Rubio ,”Efficient voice activity detection algorithms using long-term speech information,” Speech Communication, Volume 42,
Issues 3-4, April 2004, Pages271-287
[15]European Digital Cellular Telecommuni- cations System; Half rate
speech; Voice Activity Detection (VAD), ETSI GSM 06.42 (ETS
300-581-6), 1995.
[16]European Digital Cellular Telecommuni- cations System; Half rate speech; Half rate speech transcoding, ETSI GSM 06.20 (ETS 300-581-2), 1995.
[17]ITU-T G.729, Coding of Speech at 8kbit/s Using CS-ACELP, March, 1996.
[18]A. Benyassine, E. Shlomot, H. Y. Su, D. Massaloux, C. Lamblin, and J. P. Petit, “ITU recommendation G.729 annex B: A silence compression scheme for use with G.729 optimized for V.70 digital simultaneous voice and data applications,” IEEE Commun. Mag., vol. 35, pp. 64–73, Sept. 1997.
[19]Ali H. Sayed, Fundamentals of Adaptive Filtering
[20]Dahl, M.; Claesson, I., “Acoustic noise and echo cancelling with microphone array,” Vehicular Technology, IEEE Transactions on , Volume: 48 Issue: 5 , Sept.1999 Page(s): 1518 –1526
[21]Quartus II Handbook
[22]Nios II Processor Reference Handbook , ALTERA Corp.
[23]Nios II Software Development Handbook , ALTERA Corp.
[24]Stratix Device Handbook, Volume 1 , ALTERA Corp.
[25]Stratix Device Handbook, Volume 2 , ALTERA Corp.
[26]Avalon Interface Specification , ALTERA Corp.
[27]Nios Development Board Reference Manual, Stratix Professional Edition , ALTERA Corp.
[28]David Halupka ; Nebu John Mathai ; Parham Arrabi ; Sheikholeslami “Robust Sound Location in 0.18um CMOS” IEEE TRANSACTIONS ON SIGNAL PROCESSING 53 (6): 2243-2250 JUN 2005
[29]Chin-Liang Wang ”Bit-Serial VLSI Implementation of Delaed LMS Adaptive FIR Filters” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on]Volume 41, Issue 11, Nov. 1994 Page(s):768 – 772
[30]Chin-Liang Wang; Ching-Chia Chen; Che-Fu Chang”A digit-serial VLSI architecture for delayed LMS adaptive FIR filtering”Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on Volume 1, 28 April-3 May 1995 Page(s):545 - 548 vol.1
[31]Allred, D.; Krishnan, V.; Huang, W.; Anderson, D.” Implementation of an LMS adaptive filter on an FPGA employing multiplexed multiplier architecture” Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on Volume 1, 9-12 Nov. 2003 Page(s):918 - 921 Vol.1
[32]Rissa, T.; Uusikartano, R.; Niittylahti, J.” Adaptive FIR filter architectures for run-time reconfigurable FPGAs” Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on16-18 Dec. 2002 Page(s):52 – 59
[33]Dukel, B.; Rizkalla, M.E.; Salama, P.” Implementation of pipelined LMS adaptive filter for low-power VLSI applications” Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Volume 2, 4-7 Aug. 2002 Page(s):II-533 - II-536 vol.2
[34]Huang, W.; Krishnan, V.; Allred, D.; Heejong Yoo” Design analysis of a distributed arithmetic adaptive FIR filter on an FPGA” Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on Volume 1, 9-12 Nov. 2003 Page(s):926 - 930 Vol.1
[35]Allred, D.J.; Heejong Yoo; Krishnan, V.; Huang, W.; Anderson, D.V. “A novel high performance distributed arithmetic adaptive filter implementation on an FPGA”Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on
Volume 5, 17-21 May 2004 Page(s):V - 161-4 vol.5
[36]Herzberg, H.; Haimi-Cohen, R. “A systolic array realization of an LMS adaptive filter and the effects of delayed adaptation”Signal Processing, IEEE Transactions on [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on]Volume 40, Issue 11, Nov. 1992 Page(s):2799 – 2803
[37]Lan-Da Van; Wu-Shiung Feng “Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters”Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on 4-6 Dec. 2000 Page(s):399 – 402
[38]Lan-Da Van; Wu-Shiung Feng” An efficient systolic architecture for the DLMS adaptive filter and its applications”Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on Volume 48, Issue 4, April 2001 Page(s):359 - 366
[39]Yi, Y, Woods, R, Ting, LK, et al.” High speed FPGA-based implementations of delayed-LMS filters” JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 39 (1-2): 113-131 JAN-FEB 2005