臺灣博碩士論文加值系統

隨著智慧型手機、手持式及擴增實境電子產品市場的發展，CMOS元件不斷微縮以符合市場需求。在元件尺寸微縮時，仍必須維持低功耗、高效能和低成本。但是傳統的金氧半場效應電晶體會隨著尺寸的微縮下，面臨短通道效應的影響。例如：摻雜物的接面及不規則分布問題。而垂直環繞式堆疊無接面式場效應電晶體正是被用來解決上述問題的新穎元件。
本篇論文提出垂直堆疊結構奈米薄片無接面式電晶體，在相同的面積下提高電晶體有效寬度，並且降低串聯電阻，提高電晶體密度。在堆疊結構製程上，我們使用氧化薄化的方式對多晶矽通道進行薄化，此方式可以降低缺陷，之後再利用等向性濕式蝕刻方式消耗中間層絕緣層來形成Ω形狀及環繞式電晶體。第一部分是比較Ω形狀堆疊結構與鰭式堆疊結構的差異，第二部分是針對環繞式堆疊結構。
在元件特性分析，第一部分比較Ω形狀與鰭式堆疊結構，Ω形狀堆疊結構有較高的開關電流比(Ion/Ioff current ratio>107)及較低臨界擺幅(S.S.)。第二部分針對環繞式堆疊結構，閘極環繞堆疊結構有較好的控制能力，包含(Ion/Ioff current ratio>108)及臨界擺幅可達100 mV/decade， DIBL值甚至小到可以忽略，並且小尺寸元件上都保有好的控制能力，最後，我們使用Sentaurus TCAD模擬軟體來同時比較Ω形狀、鰭式及環繞式堆疊結構來分析閘極控制能力。
此篇研究中提出Ω形狀、鰭式及環繞式堆疊奈米薄片電晶體比較，其中環繞式堆疊奈米薄片電晶體閘極控制能力較好，有機會提供下個世代互補金氧半場效應電晶體(CMOS)的解決方法，並應用在未來三維堆疊結構與系統晶片(SoC)上。

With the rapid development of the market for portable products, including smart-phones and virtual reality (VR), a complementary metal oxide semiconductor (CMOS) technology must be scaled to meet market demand. The scaled transistors should meet (1) low power, (2) high performance and (3) low cost per transistor for integrated circuit (IC). But the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer a lot of challenges when feature size is being scaled down, such as junction profile and random dopant fluctuation. Therefore, the stacked nanosheet (NS) vertically junctionless field-effect-transistors (VJ-FET) have been researching for scaling device.
In this thesis, we successfully demonstrate the stacked nanosheet(NS) vertically junctionless field-effect-transistors(VJ-FET). This structure offers more Weff per active footprint and better parallel resistance, resulting in smaller total resistance. In the vertically nanosheet fabrication process, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. Then, the inter layer and the buried oxide are removed by wet etching to form Omega-gate and GAA structure. First part will show the comparison of stacked NS VJ-FET with Omega -gate and Tri-gate. Second part will discuss stacked GAA NS VJ-FET.
In the basic characteristics analysis of device, first part will show the comparison of stacked NS VJ-FET with Omega -gate and Tri-gate. The stacked NS VJ-FET with Omega -gate has higher ON/OFF current ratio up to 107 and lower S.S.(149 mV/decade). Second part will show the stacked GAA NS VJ-FET. The GAA shows the strongest gate controllability, including higher ON/OFF current ratio up to 108 , lower S.S.( 100 mV/decade) and lower DIBL which is almost ignored. The GAA can maintain good gate controllability in short channel device. Finally, we use Sentaurus TCAD to analyze gate controllability of Omega -gate, Tri-gate and GAA structure in VJ-FET.
As a result, we proposed the Omega -gate, Tri-gate and GAA structure in VJ-FET. The GAA structure shows the strongest electrical characteristics, which may offer a possible next-generation CMOS device solution and be applied in advanced system-on-chip and 3D stacked IC applications.

中文摘要 i
Abstract iii
Contents v
Table Captions vii
Figure Caption viii
Chapter 1 - 1 -
Introduction - 1 -
1-1 Challenge of Scaling Down the Device - 1 -
1-2 Introduction of 3D device - 3 -
1-3 Inversion-mode(IM) compared to Junctionless(JL) - 8 -
1-4 Motivation - 10 -
1-5 Organization of This Dissertation - 13 -
Chapter 2 - 14 -
Junctionless Mechanism - 14 -
2-1 Superiority of Junctionless Transistor - 14 -
2-2 Basic Principle of Junctionless Transistor - 15 -
2-3 Threshold voltage of Junctionless Transistor - 20 -
Chapter 3 - 22 -
Stacke dpoly-Si NS VJ-FET with Omega Gate and Tri-gate - 22 -
3-1 Device Fabrication Process: - 22 -
3-2 Images Analysis - 26 -
3-2-1 SEM image of the device structure - 26 -
3-2-2 TEM image of the device structure - 27 -
3-3 Device Electrical Analysis - 30 -
Chapter 4 - 38 -
Stacked GAApoly-Si NSJL-FET - 38 -
4-1 Device Fabrication Process: - 38 -
4-2 TEM Images Analysis - 42 -
4-3 Device Electrical Analysis - 44 -
4-4 Device Simulation and Electrical Analysis - 51 -
Chapter 5 - 54 -
Conclusion - 54 -
Reference - 55 -

Chapter 1

[1-1] IRDS, "More Moore - Logic Core Device Technology Roadmap International Roadmap for Devices and Systems," 2017 Edition Report, 2017.
[1-2] J. P.Colinge, FinFETs and Other Multi-Gate Transistors: Springer, 2008.
[1-3] S. D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M. H. Na, "Performance Trade-offs in FinFET and Gate-All Around Device Architectures for 7nm-node and Beyond," 2015 Ieee Soi-3d-Subthreshold Microelectronics Technology Unified Conference (S3s), 2015.
[1-4] N. Loubet, T. Hook, P. Montanini, C. W. Yeung, S. Kanakasabapathy, M. Guillom, et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," in 2017 Symposium on VLSI Technology, 2017, pp. T230-T231.
[1-5] C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, pp. 97-103, Feb 2010.
[1-6] C. Lee, I. Ferain, A. Kranti, N. D. Akhavan, P. Razavi, R. Yan, et al., "Short-channel junctionless nanowire transistors," in Proc. SSDM, 2010, pp. 1044-1045.
[1-7] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, et al., "Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash," in 2011 International Reliability Physics Symposium, 2011, pp. 2E.4.1-2E.4.4.
[1-8] Y. C. Cheng, H. B. Chen, C. Y. Chang, C. H. Cheng, Y. J. Shih, and Y. C. Wu, "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1-2.

[1-9] B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, et al., "Vertically Integrated Multiple Nanowire Field Effect Transistor," Nano Letters, vol. 15, pp. 8056-8061, 2015/12/09 2015.
[1-10] B. H. Lee, J. Hur, M. H. Kang, T. Bang, D. C. Ahn, D. Lee, et al., "A Vertically Integrated Junctionless Nanowire Transistor," Nano Letters, vol. 16, pp. 1840-1847, Mar 2016.


Chapter 2

[2-1] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al., "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, p. 225, 02/21/online 2010.
[2-2] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 94, p. 053511, 2009/02/02 2009.
[2-3] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, "Theory of the junctionless nanowire FET," IEEE Transactions on Electron Devices, vol. 58, pp. 2903-2910, 2011.
[2-4] P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J.-P. Colinge, "Influence of channel material properties on performance of nanowire transistors," Journal of Applied Physics, vol. 111, p. 124509, 2012/06/15 2012.
[2-5] C. W. L. J. P. Colinge, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, "Junctionless Transistors: Physics and Properties," in Semiconductor-On-Insulator Materials for Nanoelectronics Applications, F. B. Alexei Nazarov, Francisco Gamiz, J.-P. Colinge, Jean-Pierre Raskin, V.S. Lysenko, Ed., ed: SPRINGER, 2011.

[2-6] R. Yan, A. Kranti, I. Ferain, C.-W. Lee, R. Yu, N. Dehdashti, et al., "Investigation of high-performance sub-50nm junctionless nanowire transistors," Microelectronics Reliability, vol. 51, pp. 1166-1171, 2011/07/01/ 2011.



Chapter 3

[3-1] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, et al., "Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash," in 2011 International Reliability Physics Symposium, 2011, pp. 2E.4.1-2E.4.4.

Chapter 4

[4-1] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, et al., "Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash," in 2011 International Reliability Physics Symposium, 2011, pp. 2E.4.1-2E.4.4.