臺灣博碩士論文加值系統

本論文提出一新式電流源設計，不使用雙載子電晶體與電阻元件，能避免多餘的光罩成本與元件製程上所造成誤差偏移之負面影響，為全場效電晶體之設計。此電流源在考慮各種製程與電壓（1.4V~1.98V）和溫度（-40度~120度）變異時，有著極低敏感度之特性效果，在上述之最極端的條件下，此電流源之輸出電流誤差遠低於1%的變化量，有效的抵抗製程、電壓、溫度變異。此新式電流源應用於SATA III之展頻時脈產生器。在此應用中的高頻振盪器之尾電流易受到溫度變化而導致振盪器無法輸出至目標之頻率，使得整體晶片良率降低，因此利用本論文提出之具製程電壓溫度低敏感度之全場效電流源電路代替，實現了高良率、低功耗、高展頻效能的展頻時脈產生器。此晶片之輸出時脈的頻率為6GHz，晶片實現於台積電0.18um 1P6M製程，供應電壓源為1.8V，核心電路的面積為1.29×0.99mm2，而核心電路的總功耗約為20mW，中心操作頻率為6GHz並向下展開5000ppm，電磁干擾抑制可降低約20dBm。

This paper proposes a new design of current source, which is All-MOS transistor designed without bipolar transistor and resistance component. Therefore, the current source has no negative effects of extra process variation and more mask cost.Considering various processes, voltages (1.4V to 1.98V) and temperature (-400C to 1200C), in these extreme conditions the error variation of current is much lower than 1%; therefore, the current source has a low sensitivity of process, voltage, temperature variation.In traditional application, the high frequency oscillator tail current is very sensitive to temperature variation, making the chip yields fall. Therefore, this current source circuit can be applied in oscillator to solve the issue because of low sensitivity of process, voltage and temperature. Moreover, this current source help oscillator to prove high-yield, low-power and high spread spectrum performance of the spread spectrum clock generator.The output frequency of the chip is 6GHz, and this chip was fabricated in TSMC 0.18um 1P6M process. The design in this paper uses 1.8V supply voltage, and chip area is 1.29 × 0.99mm2, and the total power consumption of the core circuit is about 20mW, and center operating frequency is 6GHz and downward expansion of 5000ppm, Electromagnetic interference suppression reduced 20dBm more.

謝辭 I
中文摘要 II
英文摘要 III
目錄 IV
圖目錄 VI
表目錄 X

第一章 緒論 1
1.1研究動機與目的 1
1.2論文章節架構 2

第二章 電流源電路之先前技術探討 3
2.1傳統電流源電路 3
2.2能隙參考電壓之電流源電路 6
2.3次臨界傳導區之電流源電路 10
2.3.1操作於次臨界傳導區之電流源電路 10
2.3.2操作於次臨界傳導區之電流相減電流源電路 16
2.3.3第二種操作於次臨界傳導區之電流相減電流源電路 19
2.4利用電晶體特性補償之電流源電路 21
2.4.1利用飄移率與門檻電壓互相補償方式之電流源電路 21
2.4.2一階溫度補償電流源電路 24

第三章 具製程電壓溫度低敏感之電流源設計 26
3.1製程低敏感度之電流源設計 26
3.2電壓低敏感度之電流源設計 29
3.3溫度低敏感度之電流源設計 30
3.4啟動電路 34
第四章 全電路介紹與模擬佈局量測 35
4.1 SSCG 35
4.1.1 Phase Frequency Detector 37
4.1.2 Differential Charge Pump with CMFB 38
4.1.3 Low Pass Filter, LPF & Control Voltage Buffer 39
4.1.4 Fully Differential VCO 40
4.1.5 Low−Power Self−Resonance Divider 43
4.1.6 All−Modulus Phase Switch Divider 44
4.1.7 Sigma−Delta Modulator 45
4.2 Pre-sim模擬: 46
4.3電路佈局: 55
4.3.1類比電路佈局考量: 55
4.3.2數位電路佈局考量: 55
4.3.3 Output buffers佈局考量: 55
4.3.4 I/O and Power Line佈局考量: 55
4.3.5全電路佈局、擺放示意、腳位圖: 56
4.3.6各子電路之佈局: 58
4.4 Post-sim模擬: 63
4.5電流源電路比較表: 71
4.6量測考量: 72
4.7量測結果: 75

第五章 結論與未來展望 80
5.1結論 80
5.2未來展望 81

參考文獻 82

圖目錄
圖2-1傳統電流源電路 3
圖2-2傳統參考電流源電路之電源電壓變異模擬 5
圖2-3傳統參考電流源電路之電阻製程變異模擬(±20%) 5
圖2-4傳統參考電流源電路之溫度變異模擬(-400C~1200C) 6
圖2-5補償電壓電路 8
圖2-6使用能隙參考電壓電路之電流源電路 9
圖2-7操作於次臨界傳導區之電流源 15
圖2-8相減之電流源電路 16
圖2-9電流相減實現抵抗溫度之電流源 17
圖2-10電流相減實現抵抗製程之電流源 18
圖2-11相減之電流源電路 19
圖2-12補償電壓電路 20
圖2-13利用互相補償方式之抗溫度電流源 21
圖2-14電晶體操作於飽和區時不同溫度之電流變化 22
圖2-15一階溫度補償電流源電路 24
圖3-1具製程電壓溫度低敏感度之電流源電路 26
圖3-2 不同製程之電壓對溫度變化 27
圖3-3 電流對電源電壓之變化 29
圖3-4不同溫度之電壓對電流的變化 31
圖3-5溫度低敏感度之電流 33
圖3-6 (a)電源電壓之時間模擬 (b)啟動電路之時間模擬 34
圖4-1 SATA III展頻時脈產生器 35
圖4-2 (a)PFD架構圖(b)半電路圖 37
圖4-3具有共模迴授元件的電荷幫浦電路架構圖 38
圖4-4相位頻率偵測器與具供模回授之差動式電荷幫浦方塊圖 39
圖4-5二階對稱低通濾波器 39
圖4-6控制訊號緩衝器(CVB)電路架構 39
圖4-7利用基極對NSL進行製程補償 40
圖4-8基極補償機制之等效電阻值曲線圖 41
圖4-9具複製偏壓電路供給偏壓的BPC補償電路之延遲元件 41
圖4-10 KVCO曲線模擬(溫度為250C時) 42
圖4-11比較理想與具製程溫度低敏感度電流源KVCO曲線模擬圖(溫度變異時) 42
圖4-12電流式邏輯除頻器電路圖 43
圖4-13振盪器與除頻器接法之方塊圖 44
圖4-14多除數除頻器中的相位切換除頻器架構 44
圖4-15 1st−order SDM方塊圖 45
圖4-16具製程電壓溫度低敏感度之電流源電路(溫度變化:-400C~1200C) 46
圖4-17具製程電壓溫度低敏感度之電流源電路(電壓變化:1.4V~1.98V) 47
圖4-18具製程電壓溫度低敏感度之電流源電路(電源電壓:1.62V) 48
圖4-19具製程電壓溫度低敏感度之電流源電路(電源電壓1.8V) 48
圖4-20具製程電壓溫度低敏感度之電流源電路(電源電壓1.98V) 49
圖4-21未展頻之控制電壓VCB+與VCB−的鎖定情形(不同製程) 50
圖4-22考慮溫度時未展頻之控制電壓VCB+與VCB−的鎖定情形(不同製程) 50
圖4-23未開啟展頻之電壓控制振盪器輸出頻譜(TT) 51
圖4-24未開啟展頻之電壓控制振盪器輸出頻譜(SS) 51
圖4-25未開啟展頻之電壓控制振盪器輸出頻譜(FF) 52
圖4-26開啟展頻之電壓控制振盪器輸出頻譜(TT) 53
圖4-27開啟展頻之電壓控制振盪器輸出頻譜(SS) 53
圖4-28開啟展頻之電壓控制振盪器輸出頻譜(FF) 54
圖4-29全電路佈局圖 56
圖4-30全電路之電路擺放示意圖 56
圖4-31全電路 I/O腳位編號 57
圖4-32 PFD和Charge pump與Low pass filter之佈局圖 58
圖4-33 PFD和Charge pump與Low pass filter之佈局方塊圖 58
圖4-34 VCO之佈局圖 59
圖4-35 Prescaler之佈局圖 60
圖4-36 PSD與SDM之佈局圖 61
圖4-37 PSD與SDM之佈局方塊圖 61
圖4-38 Current Reference之佈局圖 62
圖4-39具製程電壓溫度低敏感度之電流源電路(溫度變化:-400C~1200C) 63
圖4-40具製程電壓溫度低敏感度之電流源電路(電壓變化:1.4V~1.98V) 64
圖4-41具製程電壓溫度低敏感度之電流源電路(電源電壓1.62V) 65
圖4-42具製程電壓溫度低敏感度之電流源電路(電源電壓1.8V) 65
圖4-43具製程電壓溫度低敏感度之電流源電路(電源電壓1.98V) 66
圖4-44未展頻之控制電壓VCB+與VCB−的鎖定情形(不同製程) 67
圖4-45考慮溫度時未展頻之控制電壓VCB+與VCB−的鎖定情形(不同製程) 67
圖4-46未開啟展頻之電壓控制振盪器輸出頻譜(TT) 68
圖4-47未開啟展頻之電壓控制振盪器輸出頻譜(SS) 68
圖4-48未開啟展頻之電壓控制振盪器輸出頻譜(FF) 69
圖4-49開啟展頻之電壓控制振盪器輸出頻譜(TT) 69
圖4-50開啟展頻之電壓控制振盪器輸出頻譜(SS) 70
圖4-51開啟展頻之電壓控制振盪器輸出頻譜(FF) 70
圖4-52溫度量測環境示意圖 72
圖4-53高頻量測環境示意圖 72
圖4-54電容濾波器模型 74
圖4-55儀器圖 74
圖4-56晶片照相圖 75
圖4-57電流對電壓變化之量測圖 76
圖4-58電流對溫度變化之量測圖 76
圖4-59電流對溫度變化之誤差量測圖 77
圖4-60測試PCB板正面照相圖 78
圖4-61測試PCB板反面照相圖 78
圖4-62未開啟展頻6GHz訊號之量測暫態圖 78
圖4-63未開啟展頻6GHz訊號之量測頻譜圖 79
圖4-64開啟展頻6GHz訊號之量測頻譜圖 79

表目錄
表1 Pre-sim之製程與溫度變化表格 46
表2 Pre-sim之製程與電壓變化表格 47
表3 Pre-sim之製程、電壓與溫度變化表格 49
表4 Pre-sim之EMI抑制量比較表 54
表5 I/O腳位規劃表 57
表6 Post-sim之製程與溫度變化表格 63
表7 Post-sim之製程與電壓變化表格 64
表8 Post-sim之製程、電壓與溫度變化表格 66
表9 Post-sim之EMI抑制量比較表 71
表10電流源電路規格比較表 71
表11溫度量測使用之儀器表 72
表12高頻量測使用之儀器表 74

[1]L. Vadasz and A. S. Grove, "Temperature characteristics of MOS transistors below saturation," IEEE Transactions on Electron Devices, pages 190- 192, 1966
[2]W. M. Sanscn, F. 0. Eynde, and M. Steyaen. "A CMOS Temperature-Compensated current reference," IEEE J. Solid-Stole Circuits, vol. 23, no. 3, pp. 821-824, June 1988.
[3]K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, “Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1559–1564, Oct. 2001.
[4]I. M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 7, pp. 876–884, Jul. 2001.
[5]R. Dehghani and S. M. Atarodi, “A new low voltage precision CMOS current reference with no external components,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 12, pp. 928–932, 2003.
[6]E. Camacho-Galeano, C. Galup-Montoro, and M. Schneider, “A 2-nw 1.1-v self-biased current reference in CMOS technology,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52, no. 2, pp. 61 – 65, feb. 2005.
[7]F. Fiori and P. S. Crovetti, ”A new compact temperature-compensated CMOS current reference,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 11, pp. 724-728, Nov. 2005.
[8]C. Yoo and J. Park, ”CMOS current reference with supply and temperature compensation,” in Electronics Letters, vol. 43, no. 25, pp. 1422-1424, Dec. 6 2007.
[9]A. Bendali and Y. Audet, “A 1-V CMOS current reference with temperature and process compensation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 7, pp. 1424–1429, Jul. 2007.
[10]G. Serrano and P. Hasler, “A precision low-TC wide-range CMOS current reference,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 558–565, Feb. 2008.
[11]K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 1-uW 600-ppm/0C current reference circuit consisting of subthreshold CMOS circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 9, pp. 681–685, Sep. 2010.
[12]C.H. Wang, C.F. Lin, W.B. Yang, Y.L. Lo, “Supply Voltage and Temperature insensitive current reference for 4MHz Oscillator,” the 13th ISIC, pp. 35-38, 2011.
[13]W.-B. Yang, Z.-Y. Huang, C.-T. Cheng, and Y.-L. Lo, “Temperature insensitive current reference for the 6.27 MHz oscillator,” in Proc. 13th Int. Symp. Integr. Circuits (ISIC), Dec. 2011, pp. 559–562.
[14]J. Lee and S. Cho, “A 1.4-μW 24.9-ppm/°C current reference with process-insensitive temperature compensation in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2527–2533, Oct. 2012.
[15]B. Calvo, C. Azcona, N. Medrano, and S. Celma, “1 V CMOS current references for wide-temperature range applications,” Electronics Letters, vol. 49, no. 17, pp. 1061–1063, August 2013.
[16]A. Amaravati,M. Dave,M. Baghini,D. Sharma, “800-nA process-and-voltage-invariant 106-dB psrr ptat current reference,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 60, no. 9, pp. 577–581, Sept 2013.
[17]H. Kayahan, O. Ceylan, M. Yazici, S. Zihir, and Y. Gurbuz, “Wide range, process and temperature compensated voltage controlled current source,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 5, pp. 1345–1353, May 2013.
[18]B. Calvo, C. Azcona, N. Medrano, and S. Celma, “1 V CMOS current references for wide-temperature range applications,” Electronics Letters, vol. 49, no. 17, pp. 1061–1063, August 2013.
[19]Cai Yongda, Zhou Zhijie, Wang Zhen, Lei Jianming, "Threshold-voltage-different-based CMOS voltage reference derived from basic current bias generator with 4.3 ppm/°C temperature coefficient," Electron. Letters, vol 50, pp. 505-507, Jul. 2014.
[20]Vinaya M. M, Roy Paily, Anil Mahanta, “A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 62, no. 12, pp. 2908–2919, Dec. 2015.
[21]Shifeng Zhang, Ailing Li, Yan Han, Lu Jie, Xiaoxia Han, Ray C. C. Cheung, “Temperature compensation technique for ring oscillators with tail current,” Electronics Letters, vol. 52, no. 13, pp. 1108–1110, June. 2016.
[22]Dmitry Osipov, Steffen Paul, “Temperature Compensated Beta Multiplier Current Reference Circuit,” IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1, Dec. 2016.
[23]Shailesh Singh Chouhan, Kari Halonen, “A 0.67-uW 177-ppm/0C All-MOS Current Reference Circuit in a 0.18-um CMOS Technology,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, pp. 723–727, Aug. 2016.
[24]Dong Wang; Xiao Liang Tan; Pak Kwong Chan, “A 65-nm CMOS Constant Source With Reduced PVT Variation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1373–1385, Apr. 2017.
[25]Z.X. Yang “Low-Power 6-G bit/s Spread Spectrum Clock Generator with Process Compensation Scheme,” National Taipei University. Electrical Engineering, 2014.
[26]J.H. Chen “A 6-G bit/s SATA-III SSCG Using Onion Modulation,” National Taipei University. Electrical Engineering, 2017.
[27]Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim, “A 9.3nW all-in-one bandgap voltage and current reference circuit,” IEEE International Solid-State Circuits Conference, pp. 5-9, Feb. 2017.