臺灣博碩士論文加值系統

本論文為連續漸進暫存器(SAR)類比數位轉換器(ADC)由台灣積體電路製造股份有限公司1P6M0.18um互補式金氧半製程來實現，並具有混和開關切換和校正比較器輸入偏移電壓的機制。在這裡運用了混和開關切換─結合融合式電容切換與單調式切換來節省功率消耗。除此之外，此次設計也運用了電容充放電的電荷泵之類比校正方式以及調整電容負載之數位校正方式來達到較低的偏移電壓。
利用電荷泵校正機制之10百萬赫茲連續漸進式類比數位轉換器在模擬情況為1.8V電壓源且輸入頻率為1.975百萬赫茲時，模擬結果可達66.73dB的訊號雜訊失真比與10.79
bits的有效位元數，整體功率消耗為736.23μW並且FOM為41.58fJ/conversion-step。利用可調整式電容校正機制之50千赫茲連續漸進式類比數位轉換器在模擬情況為1.8V電壓源且輸入頻率為9.876千赫茲時，模擬結果可達72.56dB的訊號雜訊失真比與11.76bits的有效位元數，整體功率消耗為18.31μW並且FOM為105.59fJ/conversion-step。
利用電荷泵校正機制之10百萬赫茲連續漸進式類比數位轉換器在1.8V電壓源和1百萬赫茲的操作頻率下，當輸入頻率為12.3444千赫茲時，量測結果為39.50dB的訊號雜訊失真比及6.27bit的有效位元數，總功率消耗為186.3762µW。

This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used.
For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step.
For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW.

摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 1
1.3 論文架構 2
第二章 類比數位轉換器概論 3
2.1 類比數位轉換器規格參數 3
2.1.1 量化誤差 3
2.1.2 解析度 4
2.1.3 訊號雜訊比 5
2.1.4 訊號雜訊失真比 5
2.1.5 無雜散動態範圍 5
2.1.6 有效位元數 6
2.1.7 偏移誤差及增益誤差 7
2.1.8 微分非線性誤差 7
2.1.9 積分非線性誤差 8
2.1.10 動態範圍 8
2.2 類比數位轉換器架構 9
2.2.1 快閃式類比數位轉換器 10
2.2.2 管線式類比數位轉換器 12
2.2.3 連續漸進式類比數位轉換器 13
2.2.4 結論 14
第三章 連續漸進式類比數位轉換器 16
3.1 連續漸進式類比數位轉換器架構 16
3.2 電容切換方式 18
3.2.1 電荷重新分佈原理 19
3.2.2 傳統式電容切換[12] 20
3.2.3 單調式切換[13] 22
3.2.4 融合式電容切換[14] 23
3.2.5 結論 25
第四章 電路設計與實現 26
4.1 系統架構圖 26
4.2 取樣保持電路 27
4.3 比較器 33
4.3.1 比較器的非理想效應 33
4.3.2 動態式比較器架構 34
4.3.3 電荷泵校正機制 35
4.3.4 可調整式電容校正機制 40
4.4 時脈產生器 43
4.4.1 D型正反器 45
4.5 數位類比轉換器 46
4.5.1 混和式切換[30] 46
4.5.2 控制邏輯 47
4.5.3 電容陣列 49
4.6 模擬結果 50
4.6.1 利用電荷泵校正機制之10百萬赫茲連續漸進式類比數位轉換器 51
4.6.2 利用可調整式電容校正機制之50千赫茲連續漸進式類比數位轉換器 55
4.6.3 電路佈局圖 60
第五章 測試考量與量測結果 63
5.1 量測環境考量 63
5.1.1 電壓調節器 65
5.1.2 印刷電路板 66
5.2 量測結果 67
5.4 量測討論 73
第六章 結論與未來展望 74
6.1 結論 74
6.2 未來展望 75
參考文獻 76

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