臺灣博碩士論文加值系統

本論文使用台積電提供之CMOS 0.18微米製程設計一個K頻段的射頻前端電路，其中呈現的電路包含：干擾拒斥之低雜訊放大器、具三個傳輸零點之二階濾波器、使用高慢波係數之傳輸線設計的九十度耦合器。干擾拒斥之低雜訊放大器是由一個疊接低雜訊放大器結合一個干擾拒斥濾波器，而在干擾拒斥濾波器中，使用一種具有高品質因子、結合非對稱性抽頭式電感與電晶體的設計電路，我們稱之為半主動式電感，此設計電路所產生的負阻抗可以補償電路中的阻抗損耗。相同地，在二階三個零點濾波器的設計中，我們也使用了此半主動式電感產生負阻，以補償電路當中的阻抗損耗，並且在輸出與輸入端之間並聯一個電感，以達到三個傳輸零點的目的，讓此濾波器具有高選擇性的特性。最後，經由改變傳輸線的地平面結構，設計具有高Q值與高慢波系數之傳輸線，並將其應用於一個九十度耦合器的設計。

實測結果：干擾拒斥之低雜訊放大器的模擬值，在22.8GHz頻段的增益、雜訊和1dB增益壓縮點分別為10.46dB、4.73dB和-12.63dBm；而功率消耗方面，低雜訊放大器與拒斥濾波器一共消耗了14.13mW，並且在17.9GHz處呈現33.46dB的拒斥深度。再來，具三個傳輸零點之濾波器之實測結果， 在23.5GHz，輸入損耗、雜訊指數、1dB增益壓縮點和功率損耗分別為16.5dB、13.2dB、-3.5dBm和4.2mW；此濾波器反射損耗為13.2dB並且3-dB頻寬比為17%，傳輸零點的拒斥超過15.2 dB。相較於一般的帶通濾波器與干擾拒斥低雜訊放大器，使用改良後半主動電感，不但有效降低了帶通濾波器的輸入損耗，還讓低雜訊放大器的干擾拒斥濾波器有更好的拒斥功能。最後，使用慢波傳輸線技術的九十度耦合器展現面積微型化的特性，晶片面積只佔了0.352 mm2，在24GHz頻段相當於0.00225個平方波長。

This thesis aims to design a K-band RF front-end using a standard mixed-signal/RF 0.18um CMOS 1P6M process provided by TSMC. The presented circuits including an image/interference-reject low noise amplifier (IR-LNA), a second-order bandpass filter (BPF) with three transmission zeros, and a 90 degree coupler using high slow-wave transmission lines. The IR-LNA consists of a cascode LNA and an image/interference rejection filter. A Q-enhanced technique called semi-active inductor using a tapped-inductor and a NMOS transistor is proposed to improve the image rejection. In order to realize the Q-enhanced inductor, a negative resistance circuit is employed to compensate the resistive losses of inductors. Similarly, the Q-enhanced technique is also employed to reduce the resistive losses of the proposed 2nd BPF. Moreover, a feedback inductor is added between input and output ports to achieve three transmission zeros offering high selectivity. Finally, the 90 degree coupler using high slow-wave transmission lines with superior performances is presented. The characteristics of the guiding structure feature high Q factor and high slow-wave factor by changing the geometry in the ground plane.
Measured results: the measured gain, NF, and P1dB at 22.8GHz of the LNA are 10.46dB, 4.73dB, and -12.63dBm, respectively. The LNA including the notch filter consumes 14.13-mW power consumption. Furthermore, it achieves a 33.46-dB image/interference rejection at 17.9 GHz. The measured insertion loss, noise figure, P1dB, and power consumption of the 2nd BPF are 1.65dB, 13.2dB, -3.5dBm, and 4.2mW at 23.5 GHz. Additionally, the filter achieves a 13.2-dB return loss with a 17% 3-dB bandwidth, and the rejection levels at these transmission zeros are greater than 15.2dB. Compared with conventional image/interference rejection filters and bandpass filters, the two designs combined with the proposed semi-active inductors not only reduce the insertion loss in filters, but also show the better rejection levels. Finally, the 90 degree coupler using the proposed slow-wave transmission line technique shows a low-loss and miniaturized design. The compact area is 0.352 mm2, and the size is merely 0.00225 square wavelenth at 24GHz.

摘要………………………………………………i
Abstract…………………………………………iii
Table of Content………………………………v
List of Tables…………………………………viiI
List of Figures………………………………iX
Chapter 1 Introduction ....................... 1
1.1 Motivation ............................... 1
1.2 List of Contributions..................... 2
1.3 Thesis Origination ....................... 3
Chapter 2 Basic in RF Theory ................. 5
2.1 Definitions of Quality Factor ............ 5
2.2 RLC Series Resonant Circuits.............. 7
2.3 RLC Parallel Resonant Circuits ........... 9
2.4 Linearity in RF Circuits ................. 11
Chapter 3 A CMOS 90o Coupler using High Slow-Wave Transmission Lines ........................... 16
3.1 Transmission Lines in 0.18-um CMOS Technology .......................... 17
3.2 Slow-Wave Transmission Lines ............. 19
3.3 Miniaturized 90o Coupler ................. 26
3.4 Simulation and Measurement of the 90o Coupler ............................. 28
Chapter 4 A CMOS Bandpass Filter With Three Finite Transmission Zeros ........................... 32
4.1 Introduction ............................. 32
4.2 Design Methodology of The Active BPF ..... 34
4.3 Q-enhanced Inductor ...................... 39
4.4 Stability and Noise Consideration ................................ 42
4.5 Implementation and Measurement of the Filter ............................. 44
Chapter 5 A CMOS Low-Noise Amplifier Using Semi-Active Inductor Topology .............................49
5.1 Overview of CMOS LNA ..................... 49
5.2 Selection of Cascode Device .............. 51
5.3 The Problem of Interference /Image .......................... 53
5.4 Semi-active Image-rejection Filter ....... 56
5.5 Simulation and Measurement of the IR-LNA ..62
Chapter 6 Conclusion ......................... 66
Reference. ................................... 67
Pulication List............................... 73

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