臺灣博碩士論文加值系統

本論文係利用電性量測技術配合technology computer aided design (TCAD)元件模擬，研究amorphous InGaZnO thin film transistor (a-IGZO TFT)與polysilicon TFT (poly-Si TFT)之相關電性模擬與元件物理機制。
首先分析實際元件量測結果，以TCAD simulator建立元件TCAD模型，再進一步研究a-IGZO塊材、源/汲極(S/D)接觸區域之載子濃度分佈對current-voltage (I-V)、capacitance-voltage (C-V)影響，同時考量缺陷能態、界面固定電荷、閘極與S/D金屬對載子濃度之影響。a-IGZO厚度改變從10 nm至140 nm，而a-IGZO層以及源/汲極接觸區之摻雜濃度改變範圍為1010 - 1020 cm-3，以上述參數獲得I-V、C-V並探討分析其能帶圖、電子濃度分佈之物理意義及機制，再經數值積分得到a-IGZO TFT通道中總電子數量，進一步研究其a-IGZO厚度與I-V、C-V特性之關係。
此外，亦進一步探討a-IGZO TFT特性受背通道表面局部缺陷(Dloc)影響之物理機制，Dloc以四個能帶之能態密度描述，於背通道表面之Acceptor-like tail與Deep-level defect states範圍為1010 cm-3 - 1020 cm-2 eV-1，並觀察其能帶彎曲、電場分佈及載子濃度分佈進行定量之探討。當a-IGZO厚度(tIGZO)為20 - 300 nm，無Dloc存在時，TFT於tIGZO 20 nm之效能最佳；反之，當Dloc存在時，TFT於tIGZO 20 nm之效能最差。
Dual gate poly-Si TFT量測分析部分，首先以變溫量測IDS-VGS之方法萃取其poly-Si之能態密度分佈，再利用TCAD simulator模擬其能態密度分佈，並進一步建立poly-Si TFT電性物理模型，進而探討雙閘極多晶矽薄膜電晶體內載子傳輸之物理機制，並分析dual gate poly-Si TFT於off-state時，其漏電流是由通道區與S/D之接觸區所造成之band-to-band tunneling所引起。

This study performed electrical measurements and technology computer aided design (TCAD) simulation, to study the physical mechanisns underlying the performances of amorphous InGaZnO thin film transistors(a-IGZO TFTs) and poly-Silicon TFTs (poly-Si TFTs).
Firstly, by analyzing measurement data of an fabricated amorphous InGaZnO thin film transistor (a-IGZO TFT) the TCAD TFT model was established to study the correlation between carrier concentration distribution, current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the a-IGZO TFTs. The equilibrium carrier concentration of the a-IGZO layer influenced by defect states, interface fixed charges, gate and S/D electrodes were studied systematically and quantitatively. The a-IGZO thickness was varied from 10 nm to 140 nm. The doping concentration in the bulk a-IGZO layer and source/drain (S/D) contact regions were changed from 1010 cm-3 to 1020 cm-3. The physical mechanisms underlying the I-V and C-V variation caused by above-mentioned parameters were explored by analyzing the energy band diagram and carrier concentration distribution in the a-IGZO layer. The total number of electrons in the channel region of the TFT was calculated by numeric integration for further investigating its correlation with the a-IGZO thickness, I-V, and C-V characteristics of the a-IGZO TFTs.
This work also investigated physical mechanisms underlying effects of localized back-surface defects (Dloc) on performances of a-IGZO TFTs. Four bands of density of states were utilized to represent the Dloc. The a-IGZO thickness (tIGZO) was varied from 20 nm to 300 nm. When the Dloc was absent, the TFT with tIGZO of 20 nm can exhibit the best TFT performance. However, it got the severest performance degradation when the Dloc was taken into consideration.
The density of states (DOS) distribution of the dual gate poly-Si TFT was extracted by measureing the IDS-VGS cures of the poly-Si TFT at temperature of 300 - 460 K. Then, six bands of DOS were utilized to represent the extracted DOS. The simulated electrical characteristic was in agreement with measured data. Then, this TCAD poly-Si TFT model was used to invertigate the band diagram, carrier distribution and carrier transport in the dual gate poly-Si TFT. The leakage current was found to be caused by the band-to-band tunneling in the channel and source/drain contact region.

摘要 i
ABSTRACT ii
誌謝 iv
目錄 v
表目錄 viii
圖目錄 ix
第一章 緒論 1
1-1 前言 1
1-2 研究動機與目的 2
第二章 元件物理與參數萃取 3
2-1 半導體薄膜介紹 3
2-1-1 非晶氧化銦鎵鋅薄膜 3
2-1-2 多晶矽薄膜 3
2-2 操作原理 5
2-3 元件特性與參數定義 6
2-3-1 次臨界擺幅 (Sub-threshold swing, S.S) 6
2-3-1 臨界電壓 (Threshold Voltage, Vth) 7
2-3-2 載子遷移率(Carrier mobility) 8
2-3-3 金屬-半導體接觸 10
2-3-4 漏電流機制 (Leakage current mechanism) 11
2-3-5 德拜長度 (Debye length) 12
2-4 TCAD物理模型介紹 13
2-4-1 基本電壓電流計算模型 13
2-4-2 物理模型(Physical Models) 16
第三章 元件模擬之方法 22
3-1 非晶氧化銦鎵鋅薄膜電晶體 22
3-1-1 a-IGZO TFT模擬電性建立 23
3-1-2 a-IGZO TFT載子濃度變化之模擬方法 23
3-1-3 a-IGZO TFT之背通道局部表面受缺陷能態影響之模擬方法 25
3-2 雙閘極多晶矽薄膜電晶體 27
3-2-1 Dual gate poly-Si TFT 之DOS計算 27
3-2-2 Dual gate poly-Si TFT之電性模型建立 28
第四章 結果與討論 30
4-1 a-IGZO TFT載子濃度之變化與I-V、C-V特性之關係 30
4-1-1. 源極與汲極金屬對載子濃度之影響 30
4-1-2. 閘極電極與閘極介電層對載子濃度之影響 34
4-1-3. DOS、摻雜濃度與固定電荷對載子濃度之影響 34
4-1-4. 模擬傳輸特性 36
4-1-5. a-IGZO bulk摻雜濃度(德拜長度)之影響 37
4-1-6. 源極與汲極接觸區摻雜濃度(德拜長度)之影響 39
4-1-7. a-IGZO厚度對I DS–VGS與CG–VGS之影響 42
4-2 a-IGZO TFT之背通道局部表面受缺陷能態影響 46
4-2-1. 未加Dloc之a-IGZO TFT 46
4-2-2. tIGZO為20 nm下，Dloc對TFT之影響 46
4-2-3. tIGZO為300 nm下，Dloc對TFT之影響 50
4-2-4. tIGZO 20-300 nm下，Dloc對TFT之影響 52
4-3 Poly-Si量測DOS與模擬分析 58
4-3-1 Poly-Si TFT之DOS計算 58
4-3-2 DOS之實驗值與模擬值分析 59
4-3-3 Poly-Si TFT之模擬與量測電性分析 61
第五章 結論 66
第六章 未來展望 67
參考文獻 68

[1]M. Januar, S. P. Prakoso, S. Y. Lan, R. K. Mahanty, S. Y. Kuo, and K. C. Liu, "The role of oxygen plasma in the formation of oxygen defects in HfOx films deposited at room temperature," Journal of Materials Chemistry C, vol. 3, pp. 4104-4114, 2015.
[2]T. Kamiya, K. Nomura, and H. Hosono, "Present status of amorphous In-Ga-Zn-O thin-film transistors," Science and Technology of Advanced Materials, vol. 11, p. 044305, Aug 2010.
[3]H. W. Zan, C. C. Yeh, H. F. Meng, C. C. Tsai, and L. H. Chen, "Achieving high field-effect mobility in amorphous indium-gallium-zinc oxide by capping a strong reduction layer," Advanced Materials, vol. 24, pp. 3509-3514, Jul 2012.
[4]C. H. Wu, K. M. Chang, S. H. Huang, I. C. Deng, C. J. Wu, W. H. Chiang, et al., "Characteristics of IGZO TFT prepared by atmospheric pressure plasma jet using PE-ALD Al2O3 gate dielectric," IEEE Electron Device Letters, vol. 33, pp. 552-554, Apr 2012.
[5]M. D. H. Chowdhury, M. Mativenga, J. G. Um, R. K. Mruthyunjaya, G. N. Heiler, T. J. Tredwell, et al., "Effect of SiO2 and SiO2/SiNx passivation on the stability of amorphous indium-gallium zinc-oxide Thin-Film transistors under high humidity," IEEE Transactions on Electron Devices, vol. 62, pp. 869-874, Mar 2015.
[6]Z. Hu, D. X. Zhou, L. Xu, Q. Wu, H. T. Xie, and C. Y. Dong, "Thermal stability of amorphous InGaZnO thin film transistors passivated by AlOx layers," Solid-State Electronics, vol. 104, pp. 39-43, Feb 2015.
[7]J. Ka, E. N. Cho, M. J. Lee, J. M. Myoung, and I. Yun, "Electrode metal penetration of amorphous indium gallium zinc oxide semiconductor thin film transistors," Current Applied Physics, vol. 15, pp. 675-678, Jun 2015.
[8]J. K. Um, S. Lee, S. Jin, M. Mativenga, S. Y. Oh, C. H. Lee, et al., "High-performance homojunction a-IGZO TFTs with selectively defined low-resistive a-IGZO source/drain electrodes," IEEE Transactions on Electron Devices, vol. 62, pp. 2212-2218, Jul 2015.
[9]A. Nathan, S. Lee, S. Jeon, I. Song, and U. Chung, "Transparent oxide semiconductors for advanced display applications," Information Display, vol. 29, pp. 6-11, 2013.
[10]M. Kim, G. Jin, K. B. Kim, and J. Song, "Effects of the single and double (overlap) scanned excimer laser annealing on solid phase crystallized silicon films," Displays, vol. 36, pp. 9-12, Jan 2015.
[11]J. H. Park, K. H. Seok, Z. Kiaee, H. Y. Kim, H. J. Chae, S. K. Lee, et al., "Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystalline-Silicon Thin-Film Transistors Fabricated via Metal-Induced Lateral Crystallization," IEEE Transactions on Semiconductor Manufacturing, vol. 28, pp. 35-40, Feb 2015.
[12]Y. C. Wang, H. Ahn, C. H. Chuang, Y. P. Ku, and C. L. Pan, "Grain-size-related transient terahertz mobility of femtosecond-laser-annealed polycrystalline silicon," Applied Physics B, vol. 97, pp. 181-185, 2009.
[13]S. Katsuya, O. Fumiaki, N. Takashi, K. HyungMo, and C. HongSock, "Influence of grain size deviation on the characteristics of poly-Si thin film transistor," Journal of the Korean Physical Society, vol. 59, pp. 298-303, 2011.
[14]Y. Morimoto, Y. Jinno, K. Hirai, H. Ogata, T. Yamada, and K. Yoneda, "Influence of the grain boundaries and intragrain defects on the performance of poly-Si thin film transistors," Journal of the Electrochemical Society, vol. 144, pp. 2495-2501, Jul 1997.
[15]M. Kimura, T. Yasuhara, K. Harada, D. Abe, S. Inoue, and T. Shimoda, "The study of oxide-interface and grain-boundary traps in poly-Si TFT characteristics and its application to fabrication process diagnosis," Journal of the Society for Information Display, vol. 13, pp. 1027-1033, 2005.
[16]S. M. Sze, Semiconductor devices physics and devices, 2nd ed.: Wiley, 2001.
[17]D. K. Schroder, Semiconductor material and device characterization, 3rd ed.: John Wiley, 2006.
[18]A. Ortiz-Conde, F. J. G. Sanchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectronics Reliability, vol. 42, pp. 583-596, Apr-May 2002.
[19]H. Klauk, U. Zschieschang, and M. Halik, "Low-voltage organic thin-film transistors with large transconductance," Journal of Applied Physics, vol. 102, p. 074514, 2007.
[20]C.-S. Li, Y.-N. Li, Y.-L. Wu, B.-S. Ong, and R.-O. Loutfy "Fabrication conditions for solution-processed high-mobility ZnO thin-film transistors," Journal of Materials Chemistry, vol. 19, pp. 1626-1634, 2009.
[21]J. H. Na, M. Kitamura, and Y. Arakawa, "High field-effect mobility amorphous InGaZnO transistors with aluminum electrodes," Applied Physics Letters, vol. 93, p. 063501, 2008.
[22]D. A. Neamen, Semiconductor physics and devices: basic principles, 4th ed.: McGraw-Hill, 2011.
[23]S. M. Sze and K. K. Ng, Physics of semiconductor devices, 3rd ed.: Wiley-Interscience, 2006.
[24]Atlas user’s manual device simulation software: Silvaco, Inc., 2013.
[25]S. Kumar, J. Singh, and J. Akhtar, Physics and Technology of Silicon Carbide Devices. InTech, 2012.
[26]J. B. Kim, C. Fuentes-Hernandez, W. J. Potscavage, X. H. Zhang, and B. Kippelen, "Low-voltage InGaZnO thin-film transistors with Al2O3 gate insulator grown by atomic layer deposition," Applied Physics Letters, vol. 94, Apr 2009.
[27]J. K. Yao, S. D. Zhang, and L. Gong, "Band offsets in ZrO2/InGaZnO4 heterojunction," Applied Physics Letters, vol. 101, p. 093508, Aug 2012.
[28]Y. Chen, J. Wu, Z. Hu, D. Zhou, H. Xie, and C. Dong, "Amorphous InGaZnO Thin Film Transistors with Wet-Etched Ag Electrodes," Ecs Solid State Letters, vol. 3, pp. Q29-Q32, 2014 2014.
[29]E. K. H. Yu, S. Jun, D. H. Kim, and J. Kanicki, "Density of states of amorphous In-Ga-Zn-O from electrical and optical characterization," Journal of Applied Physics, vol. 116, p. 154505, Oct 2014.
[30]H.-C. Lin, K.-Y. Ho, C.-C. Hsu, J.-Y. Yan, and J.-C. Ho, "Suppression of photo-leakage current in amorphous silicon thin-film transistors by n-doped nanocrystalline silicon," Journal of Physics D: Applied Physics, vol. 44, p. 475401, 2011.
[31]H. J. Kim, Q. Shao, and Y.-H. Kim, "Characterization of low-dielectric-constant SiOC thin films deposited by PECVD for interlayer dielectrics of multilevel interconnection," Surface and Coatings Technology, vol. 171, pp. 39-45, 2003.
[32]H. L. Skriver and N. Rosengaard, "Surface energy and work function of elemental metals," Physical Review B, vol. 46, pp. 7157-7168, 1992.
[33]H. Lhermite, O. Bonnaud, Y. Colin, and A.-M. Rouffet, "Analysis of the Field Effect in a Metal-Oxide-Small-Grain Poly silicon Structure-Experimentation and Modeling " IEEE Transactions on Electron Devices, vol. 35, pp. 675-683, 1998.
[34]Y.-C. Yeo, T.-J. King, and C. Hu, "Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology," Journal of Applied Physics, vol. 92, p. 7266, 2002.
[35]J.-J. Lin, P.-Y. Hsu, Y.-L. Wu, and J.-J. Jhuang, "Characteristics of polysilicon wire glucose sensors with a surface modified by silica nanoparticles/gamma-APTES nanocomposite," Sensors (Basel), vol. 11, pp. 2796-808, 2011.
[36]K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, "Amorphous oxide semiconductors for high-performance flexible thin-film transistors," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 45, pp. 4303-4308, May 2006.
[37]H. Kumomi, K. Nomura, T. Kamiya, and H. Hosono, "Amorphous oxide channel TFTs," Thin Solid Films, vol. 516, pp. 1516-1522, Feb 15 2008.
[38]S. Martin, C. S. Chiang, J. Y. Nahm, T. Li, J. Kanicki, and Y. Ugai, "Influence of the amorphous silicon thickness on top gate thin-film transistor electrical performances," Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 40, pp. 530-537, Feb 2001.
[39]D. Kong, H. Jung, Y. Kim, M. Bae, J. Jang, J. Kim, et al., "Effect of the active layer thickness on the negative bias illumination stress-induced Instability in amorphous InGaZnO thin-film transistors," Journal of the Korean Physical Society, vol. 59, pp. 505-510, Aug 2011.
[40]S. H. Rha, J. Jung, Y. S. Jung, Y. J. Chung, U. K. Kim, E. S. Hwang, et al., "Vertically integrated submicron amorphous-In2Ga2ZnO7 thin film transistor using a low temperature process," Applied Physics Letters, vol. 100, May 14 2012.
[41]L.-Y. Su, H.-Y. Lin, H.-K. Lin, and J. Huang, "Demonstration of low subthreshold swing a-InGaZnO thin film transistors," presented at the CS ManTech Conference, Boston, Massachusetts, USA, 2012.
[42]G. D. Yuan, T. W. Ng, Y. B. Zhou, F. Wang, W. J. Zhang, Y. B. Tang, et al., "P-type conductivity in silicon nanowires induced by heterojunction interface charge transfer," Applied Physics Letters, vol. 97, p. 153126, Oct 11 2010.
[43]W.-H. Lin, J.-J. Wu, M. M. C. Chou, Y.-M. Chang, and M. Yoshimura, "Charge transfer in Au nanoparticle-nonpolar ZnO photocatalysts illustrated by surface-potential-derived three-dimensional band diagram," Journal of Physical Chemistry C, vol. 118, pp. 19814-19821, Aug 28 2014.
[44]V. Schmidt, S. Senz, and U. Goesele, "Influence of the Si/SiO2 interface on the charge carrier density of Si nanowires," Applied Physics a-Materials Science & Processing, vol. 86, pp. 187-191, Feb 2007.
[45]T.-C. Fung, C.-S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, et al., "Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors," Journal of Applied Physics, vol. 106, p. 084511, Oct 15 2009.
[46]J. Guo, J. Wang, E. Polizzi, S. Datta, and M. Lundstrom, "Electrostatics of nanowire transistors," IEEE Transactions on Nanotechnology, vol. 2, pp. 329-334, Dec 2003.
[47]S. W. Tsao, T. C. Chang, S. Y. Huang, M. C. Chen, S. C. Chen, C. T. Tsai, et al., "Hydrogen-induced improvements in electrical characteristics of a-IGZO thin-film transistors," Solid-State Electronics, vol. 54, pp. 1497-1499, Dec 2010.
[48]S. Park, S. Bang, S. Lee, J. Park, Y. Ko, and H. Jeon, "The effect of annealing ambient on the characteristics of an indium-gallium-zinc oxide thin film transistor," Journal of Nanoscience and Nanotechnology, vol. 11, pp. 6029-6033, Jul 2011.
[49]K. Nomura, T. Kamiya, and H. Hosono, "Effects of Diffusion of Hydrogen and Oxygen on Electrical Properties of Amorphous Oxide Semiconductor, In-Ga-Zn-O," Ecs Journal of Solid State Science and Technology, vol. 2, pp. P5-P8, 2013.
[50]K.-S. Son, J.-S. Jung, K.-H. Lee, T.-S. Kim, J.-S. Park, Y.-H. Choi, et al., "Characteristics of double-gate Ga-In-Zn-O thin-film transistor," IEEE Electron Device Letters, vol. 31, pp. 219-221, Mar 2010.
[51]D. Ranka, A. K. Rana, R. Kumar Yadav, Y. Kamalesh, and G. Devendra, "Performance evaluation of FD-SOI MOSFETS for different metal gate work function," International Journal of VLSI Design & Communication Systems, vol. 2, pp. 11-24, 2011.
[52]S.-H. Choi and M.-K. Han, "Effect of deposition temperature of SiOx passivation layer on the electrical performance of a-IGZO TFTs," IEEE Electron Device Letters, vol. 33, pp. 396-398, Mar 2012.
[53]S. Hong, S. Lee, M. Mativenga, and J. Jang, "Reduction of negative bias and light instability of a-IGZO TFTs by dual-gate driving," IEEE Electron Device Letters, vol. 35, pp. 93-95, Jan 2014.
[54]J. S. Lee, S. Chang, S.-M. Koo, and S. Y. Lee, "High-performance a-IGZO TFT with ZrO2 gate dielectric fabricated at room temperature," IEEE Electron Device Letters, vol. 31, pp. 225-227, Mar 2010.
[55]S.-I. Oh, G. Choi, H. Hwang, W. Lu, and J.-H. Jang, "Hydrogenated IGZO thin-film transistors using high-pressure hydrogen annealing," IEEE Transactions on Electron Devices, vol. 60, pp. 2537-2541, Aug 2013.
[56]P. S. Yun, M. Naito, R. Kumagai, Y. Sutou, and J. Koike, "P-23: The contact properties and TFT structures of a-IGZO TFTs combined with Cu-Mn alloy electrodes," SID Symposium Digest of Technical Papers, vol. 42, pp. 1177-1180, 2011.
[57]R. Chen, W. Zhou, M. Zhang, M. Wong, and H.-S. Kwok, "Self-aligned indium-gallium-zinc oxide thin-film transistor with phosphorus-doped source/drain regions," IEEE Electron Device Letters, vol. 33, pp. 1150-1152, Aug 2012.
[58]Thin Film Transistors: Materials and Processes, 1st ed.: Springer, 2004.
[59]H. C. Cheng, F. S. Wang, and C. Y. Huang, "Effects of NH3 plasma passivation on N-channel polycrystalline silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 44, pp. 64-68, Jan 1997.
[60]C. L. Fan, H. L. Lai, and T. H. Yang, "Enhanced crystallization and improved reliability for low-temperature-processed poly-Si TFTs with NH3-plasma pretreatment before crystallization," IEEE Electron Device Letters, vol. 27, pp. 576-578, Jul 2006.
[61]E. Chong, Y. S. Chun, and S. Y. Lee, "Effect of trap density on the stability of SiInZnO thin-film transistor under temperature and bias-induced stress," Electrochemical and Solid State Letters, vol. 14, pp. H96-H98, 2011.
[62]J. M. Kwon, J. Jung, Y. S. Rim, D. L. Kim, and H. J. Kim, "Improvement in negative bias stress stability of solution-processed amorphous In-Ga-Zn-O thin-film transistors using hydrogen peroxide," Acs Applied Materials & Interfaces, vol. 6, pp. 3371-3377, Mar 12 2014.
[63]H. Mai Phi, D. Wang, J. Jiang, and M. Furuta, "Negative bias and illumination stress induced electron trapping at back-channel interface of InGaZnO thin-film transistor," Ecs Solid State Letters, vol. 3, pp. Q13-Q16, 2014.
[64]M. Nag, A. Bhoolokam, S. Steudel, A. Chasin, K. Myny, J. Maas, et al., "Back-channel-etch amorphous indium-gallium-zinc oxide thin-film transistors: The impact of source/drain metal etch and final passivation," Japanese Journal of Applied Physics, vol. 53, p. 111401, Nov 2014.
[65]J. B. Chang and V. Subramanian, "Effect of active layer thickness on bias stress effect in pentacene thin-film transistors," Applied Physics Letters, vol. 88, Jun 5 2006.
[66]M. Kimura and S. Imai, "Degradation evaluation of α-IGZO TFTs for application to AM-OLEDs," IEEE Electron Device Letters, vol. 31, pp. 963-965, September 2010.
[67]Y. S. Chun, S. Chang, and S. Y. Lee, "Effects of gate insulators on the performance of a-IGZO TFT fabricated at room-temperature," Microelectronic Engineering, vol. 88, pp. 1590-1593, Jul 2011.
[68]Y. Wang, X. W. Sun, G. K. L. Goh, H. V. Demir, and H. Y. Yu, "Influence of channel layer thickness on the electrical performances of inkjet-printed In-Ga-Zn oxide thin-film transistors," IEEE Transactions on Electron Devices, vol. 58, pp. 480-485, Feb 2011.
[69]G. J. Lee, J. Kim, J.-H. Kim, S. M. Jeong, J. E. Jang, and J. Jeong, "High performance, transparent a-IGZO TFTs on a flexible thin glass substrate," Semiconductor Science and Technology, vol. 29, Mar 2014.
[70]Y. Li, Y. L. Pei, R. Hu, Z. M. Chen, Y. Zhao, Z. Shen, et al., "Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric," Current Applied Physics, vol. 14, pp. 941-945, Jul 2014.
[71]M.-H. Lee, K.-H. Chang, and H.-C. Lin, "Effective density-of-states distribution of polycrystalline silicon thin-film transistors under hot-carrier degradation," Journal of Applied Physics, vol. 102, p. 054508, Sep 1 2007.