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參考文獻 1.葉怡成,類神經網路模式應用與實作,儒林圖書公司,民國八十二年二月. 2.Anthony W. and Daniel F. B., “Initial investigation into low-cost ultra-fine pitch solder printing process based on innovative laser printing technology,” IEEE transactions on electronics packaging manufacturing, pp.303-307, 1999 3.Dagli, C. et al., “Enhancing the Performance of Neural Network Models for the Wire Bonding Process,” Intelligent Engineering Systems through Artificial Neural Networks, Vol. 4, pp.1041-1047, 1994. 4.Danielsson, H., “Surface Mount Technology with Fine Pitch Components,” Chapman & Hall, New York, 1995. 5.Diane, E. K., “Machine Learning,” Training & development Journal, Vol. 44, No. 12, pp.24-29, December, 1990. 6.Dubravka, R., Vinko S., and Janeta F. P., “Solder Paste for Fine Line Printing in Hybrid Microelectronics,” Microelectronics Journal, Vol. 26, pp.441-447, 1995. 7.Ekere, N. N., Ismail, I., Lo. E. K., and Mannan, S. H., “Experimental Study of Stencil/Substrate Separation Speed in On-contact Solder Paste Printing for Reflow Soldering,” Journal of Electronics Manufacturing, Vol. 3, pp.25-29, 1993. 8.Franklin, M. F., “Constructing Tables of Minimum Aberration P n-m Design,” Technometrics, Vol. 26, No. 3, August, 1984. 9.Fujiuchi, Shin’ichi nad Toriyama, kazushige, “Collective Screen Printing for Carrier Bump and SMT Pads,” Proceedings of IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp.109-112, 1994. 10.Geman, S., Bienenstock, E., and Doursat, R., “Neural Networks and the Bias/Variance Dilemma,” Neural Computation, Vol. 4, pp.1-58, 1992. 11.He, D., Ekere, N.N., and Currie, M.A., “The Behavior of Solder Pastes in Stencil Printing with Vibrating Squeegee,” IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part C, 21, No.4, pp.317-324, 1998. 12.Henson, T., Huxhold, W., and Bowman, D., “An Enhanced Neural Network Learning Algorithm with Simulated Annealing,” Third Workshop on Neural Networks:Academic/Industrial/NASA/Defense, pp.87-94, February, 1992. 13.Hinch, S. W., “Handbook of Surface Mount Technology,” Longman Scientific and Technical, UK, 1988. 14.Hou, T. H., Lin, L., and Scott, P. D., “A Neural Network-based Automated Inspection System with an Application to Surface Mount Devices,” International Journal of Production Research, Vol. 31, No. 5, pp.1171-1187, 1993. 15.Huang, S, and Zhang, H., “Neural Networks in Manufacturing: A Survey,” IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp.177-190, 1993. 16.Hush, D. R., and Horne, B. G., “Progress in Supervised Neural Networks:What’s New since Lippmann,” IEEE Signal Processing Magazine, pp.8-39, January, 1993. 17.Huston, S., “Surface Mount Technology Market Forecasting,” Journal of Industrial Technology, Vol. 17, No. 1, pp.2-7, November 2000 to January 2001. 18.Hwang, J.S., “Solder Paste In Electronics Packaging,” Van Nostrand Reinhold, New York, 1992. 19.Itoh, M., “General Information on Solder Paste”, Technical Report, Tokyo, Japan, 1999. 20.Juran, J. M., Jurans Quality Control Handbook, McGraw-Hill, New York, 1974. 21.Kane, V. E., “Process Capability Indices,” Journal of Quality Technology, Vol. 18, pp.41-45,1986. 22.Kim, B. and May, G. S., “An Optimal Neural Network Process Model for Plasma Etching,” IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 1, pp.12-21, 1994. 23.Kruschke, J. K., and Movellan, J. R., “Benefits of gain:Speeded Learning and Minimal Hidden Layers in Back-propagation networks,” IEEE Transactions on Systems Man& Cybernetics, Vol. 21, pp.273-280, 1991. 24.Lau, J. H., “Handbook of Fine Pitch Surface Mount Technology,” Van Nostrand Reinhold, Chapter 1, New York, 1994. 25.Lee, Y.H. and Kim, S., “Neural Network Applications for Scheduling Jobs on Parallel Machines,” Computers and Industrial Engineering, Vol. 25, pp.227-230, 1993. 26.Lewis, C. D., Industrial and Business Forecasting Method, Butterworth Scientific, London, 1982. 27.Li, Y., Mahajan, R. L., and Tong, J., “Design Factors and Their Effect on PCB Assembly Yield- Statistical and Neural Network Predictive Models,” IEEE/CHMT International Electronics Manufacturing Technology Symposium, pp.353-361, 1993. 28.Lideen, J. D. and Dahl, A. O., “Printing Techniques for Fine Pitch Screen Printing,” Proceedings of the Technical Program- NEPCON West, pp. 1862-1877. 29.Liu, D. and Dong, J., “Dispatching Rule Selection Using Artificial Neural Networks for Dynamic Planning and Scheduling,” Journal of Intelligent Manufacturing, Vol. 7, pp.243-250, 1996. 30.Manko, H.H., “Soldering Handbook for Printed Circuits and Surface Mounting,” Van Nostrand Reinhold, New York, 1995. 31.Mannan, S. H.; Ekere, N. N.; Ismail, I.; and Lo, E. K., “Squeegee Deformation Study in the Stencil Printing of Solder Pastes,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology- Part A, Vol. 17, No. 3, pp.470-475, 1994. 32.Markstein, H. W., “Controlling the Variables in Stencil Printing,” Electronic Packaging & Production, Vol. 37, No. 2, pp.48-56, 1997. 33.Martinez, E. E., Smith, A. E., and Idanda, B., “Reducing Waste in Casting with a Predictive Neural Model,” Journal of Intelligent Manufacturing, Vol. 5, No. 4, pp.277-286, 1994. 34.May, G. S., Forbes, H. C., Hussain, N., and Charles, A., “Modeling Component Placement Errors in Surface Mount Technology Using Neural Networks,” IEEE Transactions on Components, Packaging, and Manufacturing Technology- Part C, Vol. 21, No. 1, January, 1998. 35.Montgomery, D. C., Introduction to Statistical Quality Control, New York, 1996. 36.Morris, J.R. and Wojcik, T., “Stencil Printing of Solder Paste for Fine-Pitch Surface Mount Assembly,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 14, No. 3, pp. 560-566, 1991. 37.Nadi, F., Agogino, A. and Hodges, D., “Use of Influence Diagrams and Neural Networks in Modeling Semiconductor Manufacturing Processes,” IEEE Transactions on Semiconductor Manufacturing, Vol. 4, pp.124-129, 1991. 38.Owen, M., “2-D and 3-D Inspections Catch Solder-Paste Problems,” Test & Measurement World, February, 2000. 39.Pan, J., Tonkay, G. L., Storer, R. H., Sallade, R. M., Leandri, D. J., “Critical Variables of Solder Paste Stencil Printing for Micro-BGA and Fine Pitch QFP,” IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp.94-101, 1999. 40.Pan, J., and Tonkay, G. L., “A Study of the Aperture filling Process in Solder Paste Stencil Printing,” Proceedings of the 1999 ASME International Mechanical Engineering Congress and Exposition, Nashville, Tennessee, November 14-19, pp.75-82, 1999. 41.Pan, J., Tonkay, G. L., Storer, R. H., Sallade, R. M., Leandri, D. J., “Experimental Study of Solder Paste Stencil Printing for Fine Pitch and Ultra-Fine Pitch QFP and BGA,” Proceedings of 13th Conference with Industry: Competing in a Global Manufacturing Environment, Lehigh University, Bethlehem, PA, USA, May 24 & 25, pp.59-66, 1999. 42.Pan, J., “Modeling and process optimization of solder paste stencil printing for Micro-BGA and fine pitch surface mount assembly,” Ph.D. dissertation, Lehigh university, 2000. 43.Ries, B., “3-D Post-Printing Inspection,” Circuits Assembly, June, pp.40-48, 1998. 44.Sabuncuoglu, I., and Gurgun, B., “A Neural Network Model for Scheduling Problems,” European Journal of Operation Research, Vol. 93, No. 2, pp.288-299, 1996. 45.Sahay, C., Head, L. M., Shereen, R. Dujari, P., Constable, J. H., and Westby, G., “Study of Print Release Process in Solder Paste Printing,” Journal of Electronic Packaging, Vol. 117, pp.230-234, 1995. 46.Sette, S., Boullart, L., and Langenhove, L., “Optimising a Production Process by a Neural Network/Genetic Algorithm Approach,” Journal of Engineering Application in Artificial Intelligence, Vol. 9, No. 6, pp.681-689, 1996. 47.Shang, J. S., and Tadikamalla, P. R., “Output Maximization of a CIM System:Simulation and Statistical Approach,” International Journal of Production Research, Vol. 31, No. 1, pp.19-41, 1993. 48.Soto, H. P., “Study of the thermal behavior of a printed circuit board during the reflow process inside a surface mount technology oven,” Master thesis, University of Puerto Rico, 1998. 49.Tsai, T., “Solder Defect Analysis,” Technical Report, Kaohsiung, Taiwan, 2000. 50.Tsai, T., Liu, S. and Yang, T., “A SMT Reflow Soldering Diagnosis System Using Neurofuzzy Approach,” International Journal of Fuzzy Systems, Vol. 3, No. 4, December, 2001. 51.Twomey, J. M., Smith, A. E., and Redfern, M. S., “A Predictive Model for Slip Resistance Using Artificial Neural Networks,” IIE Transactions, Vol. 27, pp.374-381, 1995. 52.Vaithyanathan, S. and Ignizio, J. P., “A Stochastic Neural Network for Resource Constrained Scheduling,” Computers and Operations Research, Vol. 19, pp.241-254, 1992. 53.Wada, Y., and Kawato, M., “Estimation of Generalization Capability by Combination of New Information Criterion and Cross Validation,” Proceedings of International Conference Neural Networks, Vol. 2, pp.1-6, 1991. 54.Wang, Q., Sun, X., Golden, B., DeSilets, L., Wasil, E., Luco, S., and Peck, A., “A Neural Network Model for the Wire Bonding Process,” Computers Operations Research, Vol. 20, No. 8, pp.879-888, 1993. 55.Wang, S., “An Insight into the Standard Back-propagation Neural Network Model for Regression Analysis,” International Journal of Management Science, Vol. 26, No. 1, pp.133-140, 1998. 56.Whitmore, Mark; Mackay, Colin, and Hobby, Alan, “Plastic Stencils for Bottom-Side Chip Attach,” Electronic Packaging & Production, Vol. 37, No. 13, pp.68-72, 1997. 57.Williams, R. J., and Zipser, D., “A Learning Algorithm for Continually Running Fully Recurrent Neural Networks,” Neural Computation, Vol. 1, pp.271-279, 1989. 58.Wilson, T. and Bloomfield, D., “An Optimistic Outlook for Ultra Fine Pitch-Part I,” Electronic Production, February, pp. 39-42, 1995. 59.Wray, B. A., Rakes, T. R., and Rees, L. P., “Neural Network Identification of Critical Factors in a Dynamic Just-in-time Kanban Environment,” Journal of Intelligence Manufacturing, Vol. 8, No. 2, pp.83-96, 1997. 60.Xiao, M., Lawless, K. J., and Lee, N. C., “Prospects of Solder Paste in the Ultra Fine Pitch Era,” Soldering & Surface Mount Technology, No. 15, pp.4-13, 1993. 61.Yang, T., Su C., and Feng, Y., “In Search of a Product Mix for Semiconductor Wafer Fabrication Facilities by a Combined Simulation/Neural Network Approach,” International Journal of Industrial Engineering, Vol. 8, No. 2, pp.142-149, 2001. 62.Zhang, H. C., and Huang, S. H., “Applications of Neural Networks in Manufacturing,” International Journal of Production Research, Vol. 33, No. 3, pp.705-728, 1995. 63.“Neural Computing:A Technology Handbook for Neural Works Professional II/ Plus,” Neural Ware, August, 2000.
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