臺灣博碩士論文加值系統

本論文係有關疊接式低溫度係數參考電壓電路設計。電路設計原理是利用BJT所具有的的正/負溫度係數特性參數互相補償，以實現一個具有零溫度係數的參考電壓電路。電路利用兩種架構去模擬驗證，並比較兩種電路之優缺點；相較於已知電路，本論文提出的電路具有架構簡單、較少晶片面積、不須使用運算放大器等優點。
本論文除了詳細敘述工作原理外，並使用HSPICE及LAKER電路模擬軟體以0.35微米製程進行佈局並下現實作；電路供應電壓是5V，溫度變化範圍則為-20°C-120°C。根據佈局後模擬結果，一階溫度補償後在25°C時，參考電壓輸出為3.014V，電壓變化量為2.568mV；參考電壓輸出為2.499V，電變化量為2.399mV；參考電壓輸出為1.249V，電壓變化量為1.192mV，相對消耗功率為0.293mW。而二階溫度補償後在25°C時參考電壓輸出為2.489V，溫度變化量為1.127mV；參考電壓輸出為1.273V，電壓變化量為0.589mV，相對消耗功率為0.954mW。
電路模擬結果與理論推導相符合，可證明電路的可行性。本論文提出之低溫度係數參考電壓電路可適用於汽車電子裝置，以及應用於各種數位和類比電路之中。
關鍵字:溫度係數、疊接式、電流鏡、參考電壓

This thesis is related to the design of cascade low temperature-coefficient reference voltage. The design principle is using both the positive and the negative temperature-coefficient parameters in BJT to compensate each other, and then a zero temperature-coefficient output reference voltage can be achieved. Two different circuit architectures have been simulated and discussed. As compared with the existed reference voltage circuits, the proposed circuits benefit from simpler circuit architecture, less chip area, and also there are no operational amplifiers included in the proposed circuits.
Detailed design principle has been disclosed in this thesis, and the HSPICE and LAKER simulation programs with 0.35-μm process parameters have been used to perform the layout and implement the circuits. According to the post-layout simulation results, where the supply voltage is 5V and the temperature ranges from -20°C-120°C, after first order temperature-compensation, as the output reference voltage is 3.014V, the maximum output voltage variation is 2.568mV, and when the output reference voltage is 2.495V, the maximum output voltage variation is 1.772mV, and finally if the output reference voltage is 1.249V, the maximum output voltage variation is 1.192mV. The corresponding power dissipation is 0.891mW. After second order temperature-compensation, the output reference voltage can be 2.489V with the maximum output voltage variation of only 1.127mV, and 1.127V with the maximum output voltage variation of 0.589mV. The corresponding power dissipation is 0.954mW.
All the simulation results are consistent with the theoretic analysis. The proposed low temperature-coefficient reference voltage circuits can be applied to vehicle electronic devices design and other digital and analog circuits.
Keywords: temperature coefficient, cascode, current mirror, reference voltage.

摘要............................................i
Abstract........................................ii
誌謝............................................iv
目錄............................................v
表目錄..........................................vii
圖目錄..........................................viii
符號說明........................................x
第一章 緒論.....................................1
1.1研究背景與動機................................1
1.2設計流程.....................................3
1.3研究重點.....................................5
1.4論文架構.....................................5
第二章 一階補償參考電壓電路.......................6
2.1參考電壓介紹與工作原理........................6
2.2電流源分析....................................9
2.3設計原理......................................10
第三章 二階補償參考電壓電路.......................14
3.1二階補償參考電壓介紹與工作原理.................14
3.2設計原理.....................................16
第四章 模擬與量測結果............................19
4.1設計流程.....................................19
4.2一階補償參考電壓電路佈局前模擬.................21
4.3一階補償參考電壓電路佈局後模擬結果.............27
4.4一階補償參考電壓電路佈局前/後模擬結果比較......33
4.5二階補償參考電壓電路佈局前模擬.................37
4.6二階補償參考電壓電路佈局後模擬結果.............41
4.7二階補償參考電壓電路佈局前/後模擬結果比較.......46
第五章 結論......................................50
參考文獻.........................................51
Extended Abstract...............................54
簡歷(CV).........................................57

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