臺灣博碩士論文加值系統

本論文提出二種低功率差動模式輸出參考電壓電路。該電路係利用MOSFET偏壓於次臨界區時電壓與電流的指數關係以及來完成低功率消耗特性。適當的調整NMOS電晶體操作在次臨界區可得到低功率正溫度係數與負溫度係數，適當的組合正負溫度係數可以實現零溫度係數的參考電壓電路。相較於已知電路，本論文提出電路具有低功率消耗、架構簡單與較少晶片面積等優點。本論文除了詳細敘述工作原理，並使用HSPICE及LAKER電路模擬軟體以0.35-μm和0.18-μm製程參數進行佈局前後模擬及下線製作，本論文提出之第一種是改良式CMOS參考電壓電路經由模擬得到的結果為當供應電壓是1.8V，溫度變化從-20˚C遞增至120˚C時，輸出電壓變化是2.0mV，功率消耗僅有4.5959uW，溫度係數為18.40 ppm/˚C，本論文提出第二種改良式參考電壓電路模擬結果為，當供應電壓是2.1V，溫度變化從-20˚C遞增至120˚C時，輸出電壓變化是3mV，功率消耗僅有21.516uW，溫度係數為29.22 ppm/˚C。電路模擬結果與理論推導相符合，也證明電路的可行性。本論文所提出之低功率差動模式輸出參考電壓電路可適用於醫療儀器與各種類比積體電路。

In this thesis, two low-power differential-mode reference voltage circuits have been proposed. The design principle is based on the low-power dissipation characteristic and the exponential relationship between the voltage and the current of the MOSFET in sub-threshold region, When the NMOS transistor is operating in the sub-threshold region, appropriately adjust the positive and negative temperature coefficients, a zero temperature coefficient reference voltage circuit can be realized. As compared with the existed differential mode reference voltage circuit, the proposed circuit benefits from low-power consumption, simpler circuit architecture, and less chip area. In this thesis, detailed design principle has been disclosed, also the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to do the pre-layout and post-layout simulation. According to the post-layout simulation results, under the supply voltage of 1.8V, the first proposed improved CMOS reference voltage circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2mV, the power dissipation is only 4.5959uW and the temperature-coefficient is 18.40 ppm/˚C. The simulation results of the second proposed reference voltage circuit shows that, under the supply voltage of 2.1V, the temperature is varies from -20˚C to 120˚C, the output voltage changes 3mV, the power dissipation is only 21.516uW and the temperature coefficient is 29.22 ppm/˚C.
Both the simulation results are consistent with the theoretic analysis. The proposed circuit can be applied to medical instruments and other analog circuits.

摘要---------------------------------------------------- i
Abstract----------------------------------------------- ii
目錄--------------------------------------------------- v
表目錄------------------------------------------------- vii圖目錄--------------------------------------------------- viii
符號說明------------------------------------------------- xi
第一章 緒論-------------------------------------------- 1
1.1　研究動機與目的--------------------------------------- 1
1.2　積體電路的發展背景------------------------------------ 1
1.3　論文大綱-------------------------------------------- 2
第二章 參考電壓工作原理---------------------------------- 3
2.1　簡介----------------------------------------------- 3
2.2　啟動電路與次臨界區(Sub-threshold region)特性----------- 3
2.2.1　啟動電路------------------------------------------ 3
2.2.2　次臨界區------------------------------------------ 4
2.3　傳統的MOSFET參考電壓--------------------------------- 8
2.4　CMOS參考電壓電路------------------------------------- 10
2.4.1　電路工作原理--------------------------------------- 11
2.4.2　實際佈局後模擬------------------------------------- 15
第三章 改良式CMOS參考電壓電路----------------------------- 17
3.1　改良式CMOS參考電壓電路之一----------------------------- 17
3.1.1　電路工作原理--------------------------------------- 18
3.2　使用疊接式電流鏡的參考電壓電路-------------------------- 21
3.2.1　電路的工作原理------------------------------------- 22
第四章 模擬與量測結果------------------------------------ 26
4.1　設計流程-------------------------------------------- 26
4.2　電路模擬結果----------------------------------------- 28
4.2.1　已知CMOS參考電壓電路-------------------------------- 28
4.2.2　改良式CMOS參考電壓電路------------------------------ 36
4.2.3　使用疊接式電流鏡的參考電壓電路------------------------ 45
4.3　電路晶片實現與晶片量測結果------------------------------ 54
4.3.1　已知CMOS參考電壓電路-------------------------------- 54
4.3.2　改良式CMOS參考電壓電路------------------------------ 57
第五章 結論-------------------------------------------- 67
參考文獻------------------------------------------------- 68
Extended Abstract-------------------------------------- 71
簡歷(CV)------------------------------------------------ 74

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