臺灣博碩士論文加值系統

目前的類比數位轉換器因處理訊號的取樣技巧不同，有許多不同的架構存在，低解析度(low resolution)的快閃型類比數位轉換器(FLASH ADC)屬於平行式來處理輸入訊號，故具有較佳的訊號轉換速率；於是又有串列式架構與較高解析度(6-bit以上)的管線式類比數位轉換器 (Pipe-lined ADC)，大大降低運算放大器使用數量與功率消耗，適合運用在中速度的訊號處理；另外還有利用訊號調變技巧的三角積分調變器(Sigma-Delta Modulator)來達到高解析度、低速度的應用領域，其中使用了超取樣(over-sampling)與雜訊移頻(noise shaping)兩大技巧。
本文中提出了另一種新型串列式架構，稱為虛擬快閃型(Pseudo-Flash的)電流模式類比數位轉換器，利用電流傳輸器(current conveyor)的極佳電流追蹤特性來針對輸入電流訊號作取樣動作；其中所用的主要電路如：電流鏡、電流放大器、取樣保持電路皆以電流傳輸器所組成；其電路架構與訊號取樣方式類似管線式類比數位轉換器，但卻與管線式完全不相同的取樣技巧，並且類似FLASH ADC具有一個時脈週期即可完成訊號取樣能力。
整個電路共串接了七個取樣級(1-bit/stage)與一組參考電流源(reference current source)，其中每一個取樣級包含了三個電流傳輸器與一個電流比較器，整個電路使用台積電TSMC CMOS 0.35μm mixed-signal 2P4M polycide製程技術，取樣頻率為12.5MHz，輸入訊號動態範圍0~400μA；在直流準確度上，微分非線性度+0.22∼-0.38 LSB，積分非線性度+0.5∼-0.08 LSB，總功率消耗為112.3mW，整個晶片尺寸(包含I/O Pads)總共為1.208 x 1.351 mm2。

There are many different structures existed due to analog to digital converter using different sampling methods. The Flash Analog to Digital Converter (FLASH ADC) is the parallel structure used for low resolution which can provide better sampling performance. Using series of structure of Pipe-Lined ADC would increase higher resolution (more than 6-bits) and reduce the number of comparator and power consumption which was suitable for medium speed application. Sigma-delta modulator (SDM) became another modulation method to provide the high resolution for low speed application. In using was over-sampling and noise shaping techniques.
This paper proposed a new structure of “Pseudo-Flash Current-Mode Analog to Digital Converter” which used well current tracking of current conveyer. The major circuit is altered from current conveyer such as current-mirror, current amplifier, current-mode sample-and-hold circuit. The new structure is same as pipe-lined ADC, but it is not alike all. The Pseudo-Flash like FLASH ADC can get all data in one clock cycle.
All of the circuit has connected seven sample-stages and one reference current source. Each 1-bit/stage has included three current conveyers and one comparator. The whole circuit implemented with process of TSMC CMOS 0.35μm mixed-signal 2P4M polycide. The sampling rate is 12.5MHz, DNL is -0.38~+0.22LSB, INL is -0.08~+0.5LSB, respectively total power consumption and die size are 112.3mW and 1.208x1.351mm2.

中文摘要 i
英文摘要 ii
誌 謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 序論 1
1.1 相關研究發展現況 1
1.2研究動機 2
1.3 設計流程 3
1.4 論文架構 4
第二章 傳統架構之類比數位轉換器 5
2.1 類比數位轉換器的分類 5
2.1.1 快閃式類比數位轉換器(Flash ADC) 5
2.1.2 兩步驟式類比數位轉換器(Two-Step ADC) 6
2.1.3 管線式類比數位轉換器(Pipelined ADC) 7
2.1.4 積分-三角類比數位轉換器(Sigma-Delta ADC) 9
2.2.1 動態效能參數(AC specification) 11
2.2.1.1 訊號雜訊比(SNR) 11
2.2.1.2 無寄生動態範圍(SFDR) 13
2.2.1.3 訊號對雜訊失真比(SNDR) 14
2.2.1.4 有效位元數(ENOB) 14
2.2.1.4 取樣頻率(sampling clock) 15
2.2.1.5 輸入範圍(Input Range) 15
2.2.2 靜態效能參數(DC specification) 15
2.2.2.1 偏移誤差(Offset error) 16
2.2.2.2 增益誤差(Gain error) 16
2.2.2.3 微分非線性度(DNL) 16
2.2.2.4 積分非線性度(INL) 17
第三章 電流傳輸器的設計與應用 19
3.1 簡介 19
3.2 電流傳輸器的介紹 19
3.2.1 第一代電流傳輸器(first-generation Current Conveyor) 19
3.2.2 第二代電流傳輸器(second-generation Current Conveyor) 20
3.3 電流傳輸器的設計 22
3.3.1 Output resistance 24
3.3.2 Open circuit Voltage Gain 24
3.3.3 Input Offset Voltage 24
3.3.4 Systematic Offset Voltage 25
3.4 電流傳輸器模擬結果 27
3.5 電流傳輸器其他應用 30
3.5.1 電壓放大器 30
3.5.2 電壓微分器 31
3.5.3 電壓積分器 32
3.5.4 電流放大器 33
3.5.5 電流微分器 34
第四章 虛擬快閃型類比數位轉換器 35
4.1 簡介 35
4.2 量化原理的種類 36
4.2.1 Single bit per stage converter 36
4.2.2 1.5-bit per stage converter 37
4.2.3 Multi-bit converter 38
4.3 單級子電路取樣原理 39
4.4 CCII為基礎之精準電流鏡 43
4.5 參考電流源產生器 47
4.6 參考電流切換電路 48
4.7 電流放大器 50
4.8 電流模式取樣保持電路 51
4.9 電流比較器 54
4.10 One-bit/stage電流模式類比數位轉換器 56
4.11 虛擬快閃型電流模式類比數位轉換器 59
4.11.1 Current mode 7-bit ADC的線性度模擬結果 60
4.11.2 Current mode 7-bit ADC的類比輸出結果 61
4.11.3 Current-mode 7-bit ADC線性度測試 62
4.11.4 Current-mode 7-bit ADC量化誤差頻譜 63
4.12 規格列表 64
第五章 佈局與量測 65
5.1 佈局考量 65
5.2 量測考量 67
第六章 結論 68
6.1 總結 68
6.2 未來展望 68

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