臺灣博碩士論文加值系統

本論文主要探討有兩個部分，第一部分探討的內容包含切換電容式與切換電流式之非理想效應的成因與補償；兩種切換技術並在相同條件下，進行最大訊號雜訊與失真比、晶片面積等比較。至於實際的硬體電路，在切換電容式方面，利用不受寄生電容(parasitic-insensitive)影響之切換電容式積分器來改善寄生電容所產生的非線性問題；在切換電流式方面，提出一個利用回授電路降低輸入阻抗以及共模前饋電路改善輸出共模位準的電流取樣電路。第二部分係針對切換電容式三角積分調變器，做更深入的探討，並設計一個使用雙量化法之多階多位元切換電容式三角積分調變器，雙量化法旨在取得多位元的較小量化誤差與單一位元的絕對線性回授優點，其中次類比數位轉換器(sub-ADC)則以快閃式類比數位轉換器架構來實現多位元量化作用。
本論文共設計出三個系統電路，均採用TSMC 0.18μm 1P6M互補式金氧半導體製程完成，分別為二加一階一位元切換電容式與二加一階一位元切換電流式與二加二階三位元切換電容式三角積分調變器；模擬結果顯示，在取樣頻率為5.12 MHz、超取樣率為128與頻寬為20 kHz的條件下，三個電路可得到最大訊號雜訊與失真比分別為87.3 dB、84.8 dB與96.5 dB。

This thesis focus on two topics, one is to study the cause of non-ideal effect and the compensations of switched-capacitor (SC) and switched-current (SI) technique.；In this topic, the comparison between the maximum SNDR and chip area is made under the same conditions. Moreover, a switched-capacitor parasitic-insensitive integrator is used to improve the non-idealitie which produced by parasitic capacitor in voltage mode. Conversely, we use sample-and-hold circuit which consists of both a feedback circuit is used to reduce the impedance at the input and a common-mode feedforward (CMFF) circuit to improve the common-mode offset at the output in the current mode. The other one is focused on the design of SC delta-sigma (Δ-Σ) modulator. That is, a high-order multi-bit delta-sigma modulator with dual-quantization technique is proposed in this topic. The dual-quantization technique is not only to reduce the quantization noise of multi-bit quantizer, but also to have intrinsically linear feedback of a single-bit DAC. Notify that the sub-ADC is made of a flash ADC.
In this thesis, three systems are proposed and fabricated with TSMC 0.18

摘　要 i
ABSTRACT ii
誌　謝 iv
目 錄 v
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 研究動機 1
1.2 論文章節與架構 3
第二章 三角積分調變器原理與架構 4
2.1 訊號處理系統 4
2.2 類比數位轉換器簡介 5
2.3 超取樣類比數位轉換器 8
2.3.1 三角積分類比數位轉換器：雜訊頻移技術 8
2.4 高階架構之三角積分調變器 16
2.4.1 內插架構 16
2.4.2 多級串接架構 16
2.5 雙量化法技術 18
2.5.1 Leslie-Singh架構 18
2.5.2 單一迴路雙量化架構 20
2.5.3 疊接雙量化架構 21
2.6 效能之定義 22
第三章 取樣與保持電路 24
3.1 取樣/保持電路 24
3.2 切換電容技術 25
3.3 切換電流技術 26
3.4 非理想效應 27
3.4.1 不匹配 27
3.4.2 傳輸誤差 30
3.4.3 脈衝穿透誤差 31
3.4.4 雜訊 36
3.5 非理想效應之補償 38
3.6 切換電容式與切換電流式之優缺 43
第四章 二加一階一位元三角積分調變器實現 46
4.1 系統設計流程 46
4.2 系統行為模擬 47
4.3 系統電路設計與模擬 52
4.3.1 積分器 52
4.3.1.1 切換電容式積分器 52
4.3.1.2 切換電流式積分器 58
4.3.2 比較器 64
4.3.2.1 電壓式比較器 64
4.3.2.2 電流式比較器 67
4.3.3 數位類比轉換器 69
4.3.3.1 電壓式數位類比轉換器 69
4.3.3.2 電流式數位類比轉換器 71
4.3.4 非重疊時脈產生器 72
4.3.4.1 應用於切換電容式之非重疊時脈產生器 72
4.3.4.2 應用於切換電流式之非重疊時脈產生器 74
4.4 系統電路模擬 76
4.4.1 切換電容式三角積分調變器電路模擬 76
4.4.2 切換電流式三角積分調變器電路模擬 78
第五章 具雙量化法之二加二階三位元三角積分調變器實現 80
5.1 系統行為模擬 80
5.2 系統電路設計與模擬 83
5.2.1 快閃式三位元類比數位轉換器 83
5.2.1.1 切換電容式比較器 86
5.2.1.2 編碼電路 87
5.2.2 切換電容式三位元數位類比轉換器 90
5.3 系統電路模擬 94
5.3.1 切換電容式二加二階三位元三角積分調變器電路模擬 95
第六章 晶片佈局考量與佈局 100
6.1 簡介 100
6.2 類比電路佈局考量 101
6.2.1 運算放大器的輸入差動對 101
6.2.2 電容比例匹配 103
6.2.3 分割不同的電源電壓 104
6.3 系統電路佈局 104
第七章 結論及未來研究方向 107
7.1 結論 107
7.2 未來研究方向 108
參考文獻 109

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