臺灣博碩士論文加值系統

本論文研究具電壓倍增模組之交錯式輸入並聯輸出串聯高升壓DC-DC轉換器，其電路架構是將兩組升壓型轉換器以輸入並聯輸出串聯的連接為基礎，導入含有耦合電感的電壓倍增模組疊加在輸出側，開關以相差二分之一切換週期的交錯式PWM操作，形成交錯式高升壓DC-DC轉換器。
轉換器具有以下優點：高電壓增益的達成，轉換器不必操作在極大的導通比。功率開關電壓應力遠低於輸出電壓，可使用低額定耐壓且導通電阻較小的MOSFET，以降低導通損失。轉換器輸入並聯架構，具有分擔輸入電流的效果，適合高輸入電流應用。交錯式操作，使得兩個耦合電感電流漣波相消，降低輸入電流漣波大小。耦合電感的漏電感減緩輸出二極體的反向恢復問題，而且漏電感能量能夠回收再利用，不但能提升效率，也能避免開關的電壓突波問題。
本文內容包含轉換器電路動作分析、轉換器設計考量及驅動電路設計。最後實作一組輸入電壓40 V，輸出電壓400 V，最大輸出功率1000 W，切換頻率40 kHz的轉換器，並且設計與研製穩壓控制器，使轉換器在輸入電壓變動及負載變動的情況下，仍然達到輸出穩壓性能，實作結果驗證了理論分析的正確性，轉換器最高效率可達97.44%。

An interleaved input-parallel output-series high step-up DC-DC converter with voltage multiplier module is proposed in the thesis. The circuit configuration is based on two boost converter with input-parallel output-series connection and a voltage multiplier module with two coupled-inductors is stacked on the output side. The switches are driven by the interleaved PWM operation with half switching period phase shift to form a interleaved high step-up DC-DC converter.
The advantages of the proposed converter are as follows. The converter achieves high voltage gain without operating at extreme duty ratio. The voltage stresses on the power switches are greatly lower than the output voltage such that the low-voltage-rated MOSFETs with low conducting resistors can be used to reduce the conduction losses. The parallel input connection can share the input current, reduce the conduction losses and handle large input current applications. The input current ripple is decreased by the interleaved operation. The output-diodes reverse-recovery problem can be alleviated by the leakage inductances of the coupled inductors. The leakage energy of the coupled inductors is recycled such that the voltage spikes on the switches are avoided and the efficiency is improved.
The converter operation analysis, design considerations, and driving circuit design are presented in this thesis. Finally, a 1000 W prototype converter with 40 V input and 400 V output operating at a switching frequency 40 kHz is built in the laboratory. In addition, a feedback controller is designed to diminish the effect of the variations of input voltage and load on the output voltage. The experimental results are presented to verify the theoretical analysis and the measured maximal efficiency is 97.44%.

目錄
中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 XI
第一章 緒論 1-1
1.1 研究背景與動機 1-1
1.2 研究內容與成果 1-5
1.3 研究步驟 1-7
1.4 相關論文回顧 1-9
1.5 論文大綱 1-10
第二章 高升壓轉換器之探討 2-1
2.1 應用耦合電感之高升壓轉換器 2-1
2.2 應用電壓倍增模組之交錯式高升壓轉換器 2-4
2.3 嶄新轉換器與相關文獻比較 2-10
第三章 轉換器電路分析與設計 3-1
3.1 轉換器衍生過程 3-1
3.2 轉換器電路動作分析 3-4
3.3 轉換器穩態特性分析 3-16
3.4 轉換器元件值參數設計 3-22
第四章 轉換器之驅動電路與控制器設計 4-1
4.1 驅動電路設計 4-1
4.2 控制器設計 4-4
第五章 轉換器模擬與系統實作成果 5-1
5.1 Is-Spice模擬波形與實作波形驗證 5-2
5.2 閉迴路控制系統實作成果與效率量測 5-8
5.3 元件功率損失估算 5-12
第六章 結論與未來展望 6-1
6.1 結論 6-1
6.2 未來展望 6-2
附錄A 升壓型轉換器的電壓增益及轉換效率 A-1
附錄B 不同負載之Is-Spice模擬波形與實作波形驗證 B-1
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