臺灣博碩士論文加值系統

此論文研究三種實用型CMOS差動模式輸出參考電壓電路。電路設計的原理係利用BJT具有的正/負溫度係數特性與MOSFET偏壓於弱反轉區時具有的正/負溫度係數特性，以適合的權重比例互相抵消即可組合形成零溫度係數的參考電壓。相較於現今業界已知電路，此論文所研究之實用型CMOS差動模式輸出參考電壓設計則不必應用到運算放大器，也不需要對電路中所使用的負溫度係數進行二階非線性補償，故具有結構簡易、晶片面積較少、消耗功率較低等優點。

此研究不僅闡述設計原理之外，此外更使用0.18微米製程參數進行佈局與實作，設計過程中利用HSPICE電路模擬軟體分別進行佈局前及佈局後模擬；模擬結果顯示此論文研究之實用型CMOS差動模式輸出參考電壓電路，當電源電壓分別為1.5V及2.2V，測試溫度範圍為-20°C增加到-120°C時，按照模擬結果顯示，第一種電路之輸出電壓平均約為734mV，最大輸出電壓變化量14.39mV，消耗功率約為0.288mW，溫度係數約為140ppm/°C；第二種電路之輸出電壓平均約為730mV，最大輸出電壓變化量30.673mV，消耗功率約為0.122mW，溫度係數約為300ppm/°C；第三種電路之輸出電壓平均約為763mV，最大輸出電壓變化量29.143mV，消耗功率約為0.117mW，溫度係數約為272.64ppm/°C。

觀察電路模擬結果確認與理論分析一致，可證實此論文研究之實用型CMOS差動模式輸出參考電壓設計的可能性。此論文研究之實用型差動模式參考電壓電路且可恰當應用在各種類比積體電路之中。

In this thesis, three different kinds of CMOS differential output reference voltage circuits have been proposed. The design principle is properly combine the positive temperature-coefficient and negative temperature-coefficient parameters to achieve a zero temperature-coefficient voltage. Both the positive and negative temperature-coefficients are obtained from the characteristics of the BJT and MOSFET biased in weak-inversion region. As compared with the present existed circuits, all the proposed reference voltage circuits do not use any operational amplifier in the design, and also do not need to perform the second order nonlinear compensation to the negative temperature-coefficient generation circuits, therefore they benefit from simpler circuit structure, smaller chip area and lower power consumption.

In addition to the detailed design principle disclosed in this thesis, the proposed circuits have been simulated by HSPICE simulation program with a 0.18μm process parameters. Besides, after the layout of the proposed reference voltage circuits has been finished, all the proposed circuits have been taped-out. The simulation results show that, when the power supply voltage is 1.5V and 2.2V, respectively, the temperature ranges from -20°C to 120°C, the average output voltage of the first proposed circuit is about 734mV, the maximum output voltage variation is 14.39mV, the power dissipation is 0.288mW, the temperature coefficient is about 140ppm/°C. The average output voltage of the second proposed circuit the is about 730mV, the maximum output voltage variation is 30.673mV, the power dissipation is 0.122mW, and the temperature coefficient is about 300ppm/°C. Finally, the average output voltage of the last proposed circuit is about 763mV, the maximum output voltage variation is 29.143mV, the power dissipation is 0.117mW, and the temperature coefficient is about 272.64ppm/°C.

The simulation results are consistent with theoretical analysis, it also confirm the validity of the design principles. The proposed CMOS differential output reference voltage circuits are expected to be used in the design of analog integrated circuits and other practical applications.

摘要.....i
Abstract.....ii
誌謝.....iv
目錄.....v
表目錄.....vii
圖目錄.....viii
符號說明.....x
第一章 緒論.....1
1.1 研究背景與動機.....1
1.2 設計流程.....2
1.3 研究重點.....3
1.4 論文架構.....3
第二章 參考電壓工作原理.....4
2.1 參考電壓介紹與原理.....4
2.2 正溫度係數.....6
2.3 負溫度係數.....7
2.4 弱反轉區(Sub-threshold region).....9
2.5 MOSFET參考電壓電路.....11
2.6 BJT參考電壓電路.....13
第三章 實用型CMOS差動模式輸出參考電壓設計.....16
3.1 CMOS差動模式輸出參考電壓電路.....16
3.2 CMOS差動模式輸出參考電壓電路之工作原理.....16
3.3 實用型CMOS差動模式輸出參考電壓電路.....18
3.3.1 第一種實用型CMOS差動模式輸出參考電壓電路.....19
3.3.2 第二種實用型CMOS差動模式輸出參考電壓電路.....21
3.3.3 第三種實用型CMOS差動模式輸出參考電壓電路.....24
第四章 模擬與量測結果.....26
4.1 設計流程.....26
4.2 電路模擬結果.....28
4.2.1 第一種實用型CMOS差動模式輸出參考電壓電路.....28
4.2.2 第二種實用型CMOS差動模式輸出參考電壓電路.....34
4.2.3 第三種實用型CMOS差動模式輸出參考電壓電路.....40
4.3 電路實現與晶片量測結果.....46
4.3.1 第一種實用型CMOS差動模式輸出參考電壓電路之量測結果.....46
4.3.2 第二種實用型CMOS差動模式輸出參考電壓電路之量測結果.....51
4.3.3 第三種實用型CMOS差動模式輸出參考電壓電路之量測結果.....56
第五章 結論.....61
參考文獻.....62
Extended Abstract.....64

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