臺灣博碩士論文加值系統

本論文提出一個十二位元每秒取樣五千萬次的時間交錯型逐漸趨近式類比數位轉換器。與過去的高解析度時間交錯型類比數位轉換器相比，本研究提出的使用殘值超取樣技術的時間交錯型類比數位轉換器架構，可以藉由提高各單一子通道類比數位轉換器的線性度，來改善整體時間交錯型類比數位轉換器的線性度。此架構不僅可以省去校正參考準位類比數位轉換器的使用，更可以降低校正電路的複雜度。
本設計以台積電90奈米CMOS標準1P9M製程實作晶片，核心電路面積佔685μm × 360μm。量測結果顯示，在0.9伏特電源供電，輸入頻率為五十萬赫茲，每秒分別取樣五千萬次及二千五百萬次的操作速度下，訊號雜訊比之最大值分別為60.01及60.58分貝，可推得每次資料轉換所消耗的能量分別為20.24及24.28飛焦耳。

This thesis presents a 12-bit 50-MS/s time-interleaved (TI) successive-approximation (SA; SAR) analog-to-digital converter (ADC). The proposed architecture, which combines the residue oversampling technique with the time-interleaved scheme, can improve the linearity of the overall time-interleaved ADC by enhancing the linearity of each sub-channel ADC. In comparison with early proposed high-resolution TI-SAR ADCs, this architecture can not only remove the reference sub-channel ADC utilized for calibration but also reduce the complexity of calibration circuit.
The proof-of-concept prototype was fabricated in TSMC 90-nm CMOS standard 1P9M process where the core area occupies 680μm × 360μm. With 0.9V supply and 0.5MHz input frequency, the measured peak signal-to-noise and distortion ratios (SNDRs) are 60.01dB at sampling rate of 50MS/s, and 60.58dB at sampling rate of 25MS/s. The corresponding figure-of-merits (FoMs) are 20.24fJ/conversion-step and 24.28fJ/conversion-step, respectively.

Abstract II
List of Figures VIII
List of Tables XII
Chapter 1 Introduction 1
1.1 BACKGROUND AND MOTIVATION 1
1.2 ORGANIZATION 4
Chapter 2 Fundamentals of Analog-to-Digital Converters 5
2.1 THE BASICS OF ADCS 5
2.1.1 Quantization Error 6
2.1.2 Resolution 8
2.1.3 Accuracy 9
2.2 STATIC SPECIFICATIONS 9
2.2.1 Offset Error 9
2.2.2 Gain Error 10
2.2.3 Nonlinearity 11
2.3 DYNAMIC SPECIFICATIONS 15
2.3.1 Signal-to-Noise Ratio 16
2.3.2 Signal-to-Noise and Distortion Ratio 16
2.3.3 Effective Number of Bits 17
2.3.4 Spurious Free Dynamic Range 17
2.3.5 Total Harmonic Distortion 18
2.3.6 Effective Resolution Bandwidth (ERBW) 19
2.3.7 Figure of Merit (FoM) 20
 
Chapter 3 Introduction of High-Resolution Time-Interleaved
SAR ADCs 21
3.1 TIME-INTERLEAVED ADC 22
3.1.1 The Concepts of Time-interleaved ADC 22
3.1.2 Effects of Channel Mismatches 24
3.2 THE BASICS OF SAR ADC 34
3.2.1 The Concepts of SAR Scheme 34
3.2.2 Circuit Operation of the SAR Architecture 37
3.3 RESIDUE OVERSAMPLING 41
3.3.1 Concept of Residue Oversampling 41
3.3.2 An Embodiment of a Residue Oversampling ADC 44
3.3.3 Simplified DEM 45
Chapter 4 A 12-bit 50-MS/s 4x-Interleaved SAR ADC 48
4.1 ARCHITECTURE OF THE PROPOSED TI-SAR ADC 49
4.1.1 Matlab Simulations with Noise 59
4.1.2 Matlab Simulations with Capacitor Mismatch 61
4.2 CIRCUIT IMPLEMENTATION 62
4.2.1 Clock Phase Generator 63
4.2.2 Modified Global-clock Bootstrapped Switch 64
4.2.3 Dynamic Two-stage Comparator 68
4.2.4 Mixed Switching Method 69
4.2.5 Digital Error Correction Decoder 71
4.2.6 Capacitor DAC Array 73
 
Chapter 5 Simulation and Measurement Results 77
5.1 LAYOUT AND CHIP FLOOR PLAN 77
5.2 POST-LAYOUT SIMULATION RESULT 80
5.3 GROUNDING IN PCB DESIGN 83
5.4 DIE MICROGRAPH AND MEASUREMENT SETUP 86
5.5 MEASUREMENT RESULTS 88
Chapter 6 Conclusions and Future Work 94
Bibliography 96

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