臺灣博碩士論文加值系統

本論文擬研製本地振盪訊號電路，可應用於X頻段及Ka頻段收發機中的本地振盪電路。本論文一共實現四種電路，首先使用tsmcTM 0.18 μm互補式金氧半導體製作X頻段本地振盪電路、使用tsmcTM 90 nm互補式金氧半導體製作Ka頻段本地振盪電路、與利用WINTM 0.25 μm GaN製程製作高功率及高效率本地振盪電路。
以下為本論文所實現之四種電路：
一、應用於X頻段利用疊接式耦合之四相位壓控振盪器
本電路利用疊接式耦合技術改善傳統並聯式耦合架構相位雜訊惡化之缺點，整體電路經由量測後，可調頻率為9.27 ~ 10.11 GHz (8.7%)，加入傳輸線損耗後最大輸出功率為-4.78 dBm，此時相位雜訊在1-MHz 偏移時最低為 -115.2 dBc/Hz，在供應電壓1.45 V下，功耗為9 mW，整體電路優化指標(FoM)為-185，整體晶片面積包含I/O PAD為1.096 × 0.593 mm2。
二、應用於X頻段整數型鎖相迴路
本電路包含壓控振盪器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、充電汞及迴路濾波器。利用上述電路合成一個鎖相迴路，並於章節中完整分析各子電路之用途及數學分析，分析雙轉單緩衝放大器需注意之問題，並提出了無死區相位頻率比較器之架構。當輸入參考頻率為37.5 MHz到39.2578125 MHz時輸出頻率能成功鎖定在9.6到10.05 GHz，除數設計為256，整體鎖相迴路功耗為39.2 mW，經由量測後參考突波大小為-45.7 dBc，鎖定後相位雜訊在1 MHz偏移時為-93.7 dBc/Hz，整體晶片面積包含I/O PAD為1.035 × 0.809 mm2。
三、應用於X頻段可調頻式回授型壓控振盪器
本電路在WINTM GaN 0.25 μm源極接地的限制下完成壓控振盪器之設計，並且在無可變電容模型的限制下，完成了可調頻機制之壓控振盪器。整體電路經由量測後，可調頻率為9.348 ~ 9.46 GHz，加入探針的損耗、傳輸線損耗和30 dB的衰減器後，最大輸出功率為27.89 dBm，此時相位雜訊在1-MHz偏移時最低為-121.62 dBc/Hz；在供應電壓19 V下，功耗為2204 mW，整體直流到射頻轉換效率為27.89%。整體晶片面積包含I/O PAD為2 × 1 mm2，電路優化指標FoMp及FoMposc分別為-195.49及-223.38。
四、應用於Ka頻段整數型鎖相迴路
本電路包含壓控振盪器、注入鎖定除頻器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率比較器、充電汞及迴路濾波器。利用上述電路合成一個鎖相迴路，當輸入參考頻率為103.6 MHz到108.9 MHz時輸出頻率能成功鎖定在26.52到27.88 GHz，除數設計為256，整體鎖相迴路功耗為43.9 mW，經由量測後參考突波大小為-48.9 dBc，鎖定後相位雜訊在1 MHz偏移時為-95.8 dBc/Hz，整體晶片面積包含I/O PAD為1.015 × 0.972 mm2。

This thesis developed four local oscillator (LO) circuits for the signal source of X band and Ka band transceivers. The X-band LO was realized in tsmcTM 0.18 μm technology. The Ka-band LO was ikplemented in tsmcTM 90 nm technology. The X-band high power and high efficiency was realized in WINTM 0.25 μm GaN process. The developed LO circuits are listed as follow,
A.Implementation on X-Band Quadrature Voltage Controlled Oscillator Using Cascode Coupling Technique
The circuit improves the phase noise in traditional parallel coupling technique by using cascaded-coupling topology. After measurements, the operation frequency is from 9.27 to 10.12 GHz (i.e., 8.7% tuning range). The best phase noise is -115.2 dBc/Hz at 1-MHz offset. The output power including transmission loss is -4.78 dBm. Under 1.45-V supply voltage, the power consumption is 7.72 mW which is correspondent to an FoM of -185. The chip size includes all pads is 1.096 × 0.593 mm2.
B.Implementation on X-Band Integer-N Phase Locked Loop (PLL)
The functional circuit blocks of the designed PLL include a voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of PLL. Meanwhile, we also analyze the issue of the differential-to-single buffer amplifier. The thesis adopts the phase and frequency detector with zero dead zone topology. The PLL is locked from 9.6 to 10.05 GHz when reference signal is 37.5 to 39.2578125 MHz. The division ratio is 256 and the total power consumption is 39.2 mW. The reference spur is as low as -45.7 dBc and phase noise is -93.7 dBc/Hz at 1-MHz offset. The chip size includes all pads is 1.035 × 0.809 mm2.
C.Implementation on X-Band Tunable Feedback Type Voltage Controlled Oscillator
The implementation on the VCO is realized in WINTM 0.25 μm GaN process under the constraint of the via-hole at source node that makes common source topology can be only adopted. Meanwhile, no varactor model is available. After measurements, the tuning frequency is from 9.348 to 9.46 GHz, and the output power including the transmission line loss and a 30-dB attenuator is 27.89 dBm. The best phase noise is -121.62 dBc/Hz at 1-MHz offset frequency. Under the 19-V supply voltage, the total power consumption is 2204 mW. The DC-to-RF conversion efficiency is 27.89%. The FoMp and FoMposc are -195.49 and -223.38, respectively. The chip size includes all pads is 2 × 1 mm2.
D.Implementation on Ka-Band Integer-N Phase Locked Loop (PLL)
The functional blocks of PLL include a VCO, an injection locked frequency divider, a current mode logic divider, a differential-to-single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. The PLL is locked from 26.52 to 27.88 GHz when reference signal is 103.6 to 108.9 MHz. The division ratio is 256 and the total power consumption is 43.9 mW. The reference spur is -48.9 dBc and phase noise is -95.8 dBc/Hz at 1-MHz offset when PLL is locked. The chip size includes all pads is 1.015 × 0.972 mm2.

摘要 I
Abstract III
誌謝 V
目錄 VII
圖目錄 IX
表目錄 XIII
第一章 緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節敘述 2
第二章 應用於X頻段利用疊接式耦合之四相位壓控振盪器 3
2-1 四相位壓控震盪器簡介 3
2-2 疊接式耦合技術架構簡介 4
2-3 四相位壓控振盪器電路架構簡介 7
2-4 量測與模擬結果 11
2-5 結果與討論 18
第三章 應用於X頻段鎖相迴路 20
3-1 鎖相迴路架構簡介 20
A. 壓控振盪器 21
B. 除頻器 21
C. 相位頻率比較器 22
D. 充電汞 23
E. 迴路濾波器 24
3-2 鎖相迴路閉迴路分析 25
3-3 鎖相迴路架構及各子電路分析 29
3-3-1 壓控振盪器 30
3-3-2 電流模式邏輯除頻器 38
3-3-3 雙轉單緩衝放大器 39
3-3-4 真單一相位時脈除頻器 43
3-3-5 全擺幅緩衝器 45
3-3-6相位頻率比較器 46
3-3-7 充電汞 49
3-3-8 迴路濾波器 52
3-4 量測與模擬結果 55
3-5 結果與討論 62
第四章 應用於X頻段可調頻式回授型高功率壓控振盪器 64
4-1 功率振盪器簡介 64
4-2 回授型壓控振盪器電路架構簡介 65
4-2-1 壓控振盪器電路設計流程 66
4-2-2 功率放大器電晶體挑選 67
4-2-3 功率放大器各元件挑選 68
4-2-4 回授型壓控振盪器電路設計 74
4-3 量測與模擬結果 77
4-4 結果與討論 83
第五章 結論 85
5-1 結論 85
5-2 未來方向 86
附錄 應用於Ka頻段整數型鎖相迴路 87
6-1 鎖相迴路架構及各子電路分析 87
6-1-1 壓控振盪器 88
6-1-2 注入鎖定除頻器 96
6-1-3 電流模式邏輯除頻器 100
6-1-4 雙轉單緩衝放大器 101
6-1-5真單一相位時脈除頻器 103
6-1-6 全擺幅緩衝器 104
6-1-7 相位頻率比較器 105
6-1-8 充電汞 107
6-1-9 迴路濾波器 110
6-2 量測與模擬結果 113
6-3 結果與討論 117
參考文獻 119

[1] A. W. L. Ng and H. C. Luong, "A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling," IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1933-1941, 2007.
[2] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, "A 900 MHz CMOS LC-oscillator with quadrature outputs," in 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, pp. 392-393.
[3] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, "Analysis and design of a 1.8-GHz CMOS LC quadrature VCO," IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, 2002.
[4] Y. Lo and J. Silva-Martinez, "A 5-GHz CMOS LC Quadrature VCO With Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy," IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 7, pp. 2632-2640, 2013.
[5] A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, 1998.
[6] J. Wu, H. Wu, K. Hsu, and C. Chen, "A Back-Gate Coupling Quadrature Voltage-Control Oscillator Embedded With Self Body-Bias Schema," IEEE Microwave and Wireless Components Letters, vol. 23, no. 3, pp. 146-148, 2013.
[7] H. Chen, D. Chang, Y. Juang, and S. Lu, "A Low Phase-Noise 9-GHz CMOS Quadrature-VCO using Novel Source-Follower Coupling Technique," in 2007 IEEE/MTT-S International Microwave Symposium, 2007, pp. 851-854.
[8] B. Jiang and H. C. Luong, "A 7.9-GHz Transformer-Feedback Quadrature Oscillator With a Noise-Shifting Coupling Network," IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2636-2646, 2017.
[9] W. Chen, M. E. Inerowicz, and B. Jung, "Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 12, pp. 936-940, 2010.
[10] J. Tsai, C. Hsu, and C. Chao, "An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology," in 2015 10th European Microwave Integrated Circuits Conference (EuMIC), 2015, pp. 238-241.
[11] K. Ha, J. Lee, S. Park, and D. Baek, "A dual-mode signal generator using PLL for X-band radar sensor applications," in 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2017, pp. 4-6.
[12] J. Tsai, C. Chao, and H. Shih, "A X-band fully integrated CMOS frequency synthesizer," in 2012 Asia Pacific Microwave Conference Proceedings, 2012, pp. 1226-1228.
[13] S. Min, T. Copani, S. Kiaei, and B. Bakkaloglu, "A 90nm CMOS 5GHz ring oscillator PLL with delay-discriminator based active phase noise cancellation," in 2012 IEEE Radio Frequency Integrated Circuits Symposium, 2012, pp. 173-176.
[14] S. Jeon, A. Suarez, and D. B. Rutledge, "Nonlinear Design Technique for High-Power Switching-Mode Oscillators," IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 10, pp. 3630-3640, 2006.
[15] H. Chang, C. Lin, Y. Liu, W. Li, and Y. Wang, "A 2.5 GHz High Efficiency High Power Low Phase Noise Monolithic Microwave Power Oscillator," IEEE Microwave and Wireless Components Letters, vol. 25, no. 11, pp. 730-732, 2015.
[16] S. Jee, J. Moon, J. Kim, J. Son, and B. Kim, "Switching Behavior of Class-E Power Amplifier and Its Operation Above Maximum Frequency," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, pp. 89-98, 2012.
[17] C. Lin, W. Li, and H. Chang, "A fully integrated 2.4-GHz 0.5-W high efficiency class-E voltage controlled oscillator in 0.15-µm PHEMT process," in Asia-Pacific Microwave Conference 2011, 2011, pp. 864-867.
[18] H. Liu, X. Zhu, C. C. Boon, X. Yi, M. Mao, and W. Yang, "Design of Ultra-Low Phase Noise and High Power Integrated Oscillator in 0.25 μm GaN-on-SiC HEMT Technology," IEEE Microwave and Wireless Components Letters, vol. 24, no. 2, pp. 120-122, 2014.
[19] S. Lai et al., "Low Phase Noise GaN HEMT Oscillators With Excellent Figures of Merit," IEEE Microwave and Wireless Components Letters, vol. 24, no. 6, pp. 412-414, 2014.
[20] Z. Q. Cheng, Y. Cai, J. Liu, Y. Zhou, K. M. Lau, and K. J. Chen, "A low phase-noise X-band MMIC VCO using high-linearity and low-noise composite-channel Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMTs," IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 1, pp. 23-29, 2007.
[21] H. Chang, C. Lin, Y. Liu, W. Li, and Y. Wang, "A K-Band High Efficiency High Power Monolithic GaAs Power Oscillator Using Class-E Network," IEEE Microwave and Wireless Components Letters, vol. 27, no. 1, pp. 55-57, 2017.
[22] Y. Chen, M. Li, T. Huang, and H. Chuang, "A V-Band CMOS Direct Injection-Locked Frequency Divider Using Forward Body Bias Technology," IEEE Microwave and Wireless Components Letters, vol. 20, no. 7, pp. 396-398, 2010.
[23] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, 2004.
[24] J. Cheng, J. Tsai, and T. Huang, "Design of a 90.9% Locking Range Injection-Locked Frequency Divider With Device Ratio Optimization in 90-nm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 1, pp. 187-197, 2017.
[25] J. Cheng, M. Wu, H. Huang, Y. Wu, J. Tsai, and T. Huang, "A K-band phase-locked loop in 0.18 μm CMOS technology for vital sign detection radar," in 2014 IEEE MTT-S International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications (IMWS-Bio2014), 2014, pp. 1-3.
[26] C. Yu, J. Tsai, and T. Huang, "A low-power Ka-band frequency synthesizer with transformer feedback VCO embedded in 90-nm COMS technology," in 2013 IEEE International Wireless Symposium (IWS), 2013, pp. 1-4.
[27] J. Lee, S. Lee, H. Kim, and H. Yu, "A 28.5–32-GHz Fast Settling Multichannel PLL Synthesizer for 60-GHz WPAN Radio," IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 5, pp. 1234-1246, 2008.
[28] Y. Chen, Y. Yu, and Y. E. Chen, "A 0.18-µm CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration," IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 551-553, 2013.
[29] 曾紹齊, “Implementations on Dual-band CMOS Quadrature Voltage Controlled Oscillator Using 4th Order Resonator, 5 GHz Gm-boosted VCO with Integrated Frequency Divider and X-band Quadrature Phase Locked Loop,” 碩士論文, 中央大學2016.
[30] 林書佑, “Complementary Self-Injection-Coupled Quadrature Voltage Controlled Oscillator, X-band VCO with Integrated Frequency Divider and X-band Phase Locked Loop,” 碩士論文, 中央大學2017.
[31] 詹凱鈞, “Implementations on C-band CMOS Low Phase Noise Class-C Voltage Controlled Oscillator, Transformer-coupled Quadrature Voltage Controlled Oscillator, C-band Integer-N Phase Locked Loop with Class-F Voltage Controlled Oscillator and X-band III-V Power Oscillators,” 碩士論文, 中央大學2018.
[32] 劉深淵，楊清淵，鎖相迴路，滄海書局，民國一百年。