臺灣博碩士論文加值系統

本論文旨在製作一適用於VDSL網路系統，且操作頻率為200 MHz之CMOS數位發射機，主要包含有12位元200MHz之數位類比轉換器及電流模式全差動線驅動器兩個部份，並採用TSMC 0.18 μm 1P6M CMOS製程技術來實現。
為了達到高速操作頻率的需求，故採用電流切換式之數位類比轉換器架構。本論文使用區段式數位類比轉換器來實現，以3位元二進制碼加上9位元溫度計碼，合成12位元數位類比轉換器。再利用緩衝器的概念，於電流源的輸出端加上一緩衝器，及配合門閂電路將各區段波形匹配，以降低突波現象。此外，為了將數位電路之佈局面積與複雜度做最佳化之設計考量，本論文將9位元之溫度計碼拆為3位元加6位元的溫度計碼解碼架構，以減少數位解碼電路的面積。在佈局方面，為了減少消除梯度效應及線性誤差，使用電流源陣列。最後實現輸出最大電流、INL及DNL分別為4095 μA，0.32及0.39 之12位元數位類比轉換器。
就線驅動器而言，為了產生較高的功率效益(Power Efficiency)，分別利用兩條不同的電壓源路徑，以避免電壓源路徑疊加，藉以實現低電壓的電路設計，以及採用合成(Synthesis)的方式，此合成電路能產生輸出阻抗匹配電阻，藉以降低電路的功率消耗、提升功率效益。此外，本論文進而利用濾波電容及對大寄生電容端點提供前饋的充放電路徑以及線驅動器後級加上電流回授補償電路，以抑制諧波失真問題，並提高線性度。本線驅動器在1.8 V的供應電壓下，能驅動100 Ω輸出端負載，產生100 MHz與2 VPP的電壓訊號振幅。

This thesis describes the chip implementation of a 200 MHz CMOS digital transmitter based on VDSL system specification. which is composed of a 12-bit, 200 MHz digital to analog converter, and a fully differential current-mode line driver. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology.
For high-speed application, the digital to analog converter adopts the switch-current mode architecture. This is a 12-bit digital-to-analog converter (DAC) is implemented with M-bit segmented, which is implemented with 3-bit binary and 9-bit unary. Buffers are used to isolate the output of digital circuit and to reduce the glitch of current. Furthermore, in case of achieving small layout area, reducing the complexity of digital circuit, 9-bit unary is composed with the 3-bit and 6-bit thermometer-encoding architecture. In order to mitigate the process variation and linear error, current source array (CSA) is applied. The simulation of 12-bit DAC shows that the max current is 4095 μA, the integral nonlinearity (INL) and the differential nonlinearity (DNL) are 0.32 LSB and 0.39 LSB respectively.
In order to have high power efficiency, in line driver the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is introduced used to reduce the crossover distortion; and that the current-feedback circuit is added to increase linearity. According to the simulation result the output voltage of the proposed line driver is 2 VPP at differential load of 100 Ω, the power supply of 1.8 V and the operating frequency of 100 MHz.

摘　要 i
ABSTRACT ii
誌 謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 數位類比轉換器 3
2.1 簡介 3
2.1.1規格之定義 4
2.2 電阻串式數位類比轉換器 5
2.3 電容式數位類比轉換器 5
2.4 電流切換式數位類比轉換器 6
2.4.1 二進位制數位類比轉換器 6
2.4.2 等電流源數位類比轉換器 7
2.4.3 區段式數位類比轉換器 8
2.5 數位輸入碼最佳化之配置考量 9
2.6 三位元二進位制之數位類比轉換器架構與設計 12
2.7 電流源電路 13
2.7.1電流源輸出阻抗技術 14
2.7.2 擁有抗製程變因之偏壓電流源 14
2.7.3 開關切換時電流源產生之突波 15
2.7.4 低臨限電壓栓鎖電路 19
2.8 九位元溫度計碼解碼與對稱矩陣式電流源佈局 20
2.8.1矩陣式電流源佈局 21
2.8.2 電流源矩陣解碼電路與溫度計碼解碼器 22
2.8.3 等效九位元溫度計碼 25
2.9 數位類比轉換器模擬結果 28
第三章 線驅動器 34
3.1 線驅動器之簡介與設計考量 34
3.2 線驅動器之基本原理及架構 34
3.2.1 線驅動器之驅動方式 34
3.2.2 全差動電流回授模式之線驅動器 36
3.3 低電壓線驅動器 38
3.3.1 誤差放大器之架構 38
3.3.2 使用誤差放大器架構實現低電壓線驅動器 40
3.4 阻抗匹配之設計 41
3.4.1 抗匹配之原理 41
3.4.2 阻抗匹配之電路實現於線驅動器 43
3.4.3 線驅動器共模回授電路實現 45
3.5 利用合成技術來實現低電壓線驅動器 45
3.6 諧波失真抑制之設計 46
3.6.1 電流回授補償電路改善諧波失真之設計 46
3.6.2 前饋電容抑制諧波失真之設計 49
3.7 線驅動器之模擬結果 51
第四章 數位發射機 57
4.1 數位發射機之簡介 57
4.2 數位類比轉換器之偏壓電路設計 58
4.2.1 定電流分散式偏壓電路 58
4.2.2 寬擺幅定電導之偏壓電路 59
4.2.3 分散式偏壓電路 62
4.3 線驅動器之偏壓電路設計 63
4.4 數位發射機之模擬結果 63
第五章 數位發射器電路佈局與量測考量 65
5.1 簡介 65
5.1.1 數位類比轉換器佈局規劃圖 66
5.2 測量考量 67
5.3 整體佈局圖 69
第六章 結論與未來研究方向 70
6.1 結論 70
6.2 未來研究方向 71
參考文獻 72

[1]M. Pelgrom, “A 50 mhz 10-bit CMOS Digital-to-Analog Converter with 75 ohm Buffer,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1990, pp. 200–201.
[2]D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997.
[3]C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948–1958, December 1998.
[4]Zhong Shupeng, Tan N. “A 12-bit 150-MSample/s Current-Steering DAC” IEEE Asia Pacific Conference on Circuits and Systems. Nov. 2008.pp. 145 - 148
[5]A. Cremonesi, F. Maloberti, and G. Polito, “A 100-MHz CMOS DAC for video-graphic systems,” IEEE Journal of Solid-State Circuits, vol. 24, no. 3, , June 1989. pp. 635–639
[6]H. Takakura, M. Yokoyama, and A. Yamaguchi, “A 10 bit 80 MHz Glitchless CMOS D/A Converter,” IEEE Custom Intergrated Circuit Conference, May 1991, pp. 26.5.1-26.5.4.
[7]T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80- MHz 8-bit CMOS D/A Converter,” IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 983–988, November 1986.
[8]J. Bastos, A. M. Marques, S. J. Steyaert, and W. Sansen, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1959–1969, December 1998.




[9]S.-Y. Chin and C.-Y. Wu, “A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources,” IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1374-1380, November 1994.
[10]E. Sackinger and W. Guggenbuhl, “A high-swing, high-impedance MOS cascode circuit,” IEEE Journal of Solid-State Circuits, vol.25, no. 1, pp. 289-298, February 1990.
[11]Jen-Hung Chi, Shih-Hsuan Chu, “A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC,” 2010 Proceedings of the ESSCIRC, pp. 222, 14-16 Sept. 2010.
[12]J. Deveugele, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen, “A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC,” IEEE Transactions on Circuits and Systems, vol. 51, no. 1, pp. 191-195 January 2004.
[13] S. Ramasamy, B. Venkataramani, “The design of an area efficient segmented DAC,” 2010 International Conference on Signal and Image Processing (ICSIP), 15-17 Dec. 2010
[14]朱陳糧，應用於IEEE 802.11a之10位元100MSs數位類比轉換器實現，碩士論文，國立交通大學電機資訊學院電機與控制學程碩士班，新竹，2005。
[15]B. Nauta and M. B. Dijkstra, “Analog Line Driver with Adaptive Impedance Matching,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1992-1998, December 1998.
[16]J. N. Babanezhad, “A 100-MHz, 50 ohm , −45-dB Distortion, 3.3-V CMOS Line Driver for Ethernet and Fast Ethernet Networking Application,” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 1044-1049, August 1999.
[17]H. Khorramabadi, “A CMOS Line Driver with 80-dB Linearity for ISDN Applications,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 539–544, April 1992.
[18]F. You, S. H. K. Embadi, and E. Sanchez-Sinencio, “Low-Voltage Class AB Buffer with Quiescent Current Control,” IEEE Journal of Solid-State Circuits, vol. 33, no. 6, pp. 915–920, June 1998.

[19]蔡乙仲，CMOS 125 MHz 雙絞線發射機，碩士論文，國立交通大學電子工程學系電子研究所，新竹，2002。
[20]R. Mahadevan and D. Johns, “A Differential 160-MHz Self-Terminating Adaptive CMOS Line Driver,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 1889–1894, December 2000.
[21]L. Jinup, N. Sungwon, K. Kwangoh, and C. Joongho “A 3.3-V ISDN U-Interface Line Driver With a New IQ-Control Circuit,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, August 2003.
[22]Seo Dongwon , G.H McAllister,. “ A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter, ” IEEE Journal of Solid-State Circuits, March 2007, pp. 486-495.
[23]R. J. Baker, CMOS Mixed Signal Circuit Design, New York: John Wiley & Sons, 2002.
[24]林意屏，125 MHz 10 位元之CMOS數位發射器，碩士論文，國立交通大學電子工程學系電子研究所，新竹，1999。
[25]姚學儒，切換電容式三角積分調變器設計與實作，碩士論文，國立臺北科技大學電機工程系研究所，台北，2007。
[26]K O''Sullivan, C Gorman, M Hennessy, “ A 12-bit 320-MSample/s Current-Steering CMOS D/A Converter in 0.44 mm2, ” IEEE Journal of Solid-State Circuits, pp. 1064 – 1072, July 2004
[27]李南曄，適用於十億位元乙太網路系統之10位元125MHz數位發射器
，碩士論文，國立臺北科技大學電機工程系研究所，台北，2009。