臺灣博碩士論文加值系統

現代化3C電子產品皆須藉由表面黏著技術(Surface mount technology, SMT)之製程所產出。SMT製程包含三個主要製造程序：(1) 鋼版錫膏印刷(Solder paste stencil printing)、零件黏貼(Component placement)、及迴焊作業(Solder reflow)。根據文獻與工業報告顯示，平均約60%之最終焊接缺點(Soldering defect)係來自於錫膏印刷製程品質不良，一般工程師常針對特定錫膏印刷缺點，會利用自身製程經驗與試誤法以解決製程問題，但製程診斷過程常過於冗長，所以導致產線長時間停擺與失去許多有效生產時間。錫膏印刷製程中，以薄型四方平坦元件(Thin quad plat package, TQFP)佔有極高之印刷缺點比率，為了快速偵測TQFP之印刷體積量，以利於嚴密監控此零件體積量之適當性，本研究利用錫膏印刷機台參數，並結合實驗設計資料、及錫膏印刷檢測資料，考量並發展三個TQFP錫膏體積量之線性與非線性之預測模型，包括多元迴歸(Multiple regression)、類神經網路(Neural network)、及迴歸樹模型，並比較三者之預測準確度。本研究結果顯示迴歸樹提供較佳的預測準確度與反應機台參數的動態變化，此研究可做為工業4.0智慧製造之基礎與作為業界之參考與應用。

Surface mount technology (SMT) is the main process to produce many types of modern electronics products in electronics assembly industry. SMT consists of three sub-processes: (1) solder paste stencil printing, (2) component placement, and (3) solder reflow. Based on literatures and industrial reports, a poor solder paste printing performance can lead to an averaged 60% of soldering defect, which increases manufacturing costs and jeopardizes product quality. Generally, engineers integrate their working experience with a variety of trial-and-error approaches to resolve stencil printing problems. However, this process troubleshooting approach also induces a lot of nonproductive production time and costs. The thin quad plat package (TQFP) is with the highest stencil printing defect rate in SMT process. In this research, three solder paste volume prediction models include multiple regression, regression tree, and neural network were developed using the experimental data, the parameter settings of stencil printer, and solder paste inspection data, to quickly predict the solder paste volume of a TQFP package. These three prediction models were validated and evaluated using empirical data collected from production line. The evaluation result shows that regression tree model exhibits a superior prediction accuracy and dynamic changes of printing parameters. This research results can be used as the basis of smart manufacturing and as a reference and application in the electronics assembly industry.

目錄 I
圖目錄 III
表目錄 V
摘 要 1
Abstract 1
第一章 前言 2
1.1 研究動機 3
1.2 研究前提與限制 4
1.2.1 研究前提 4
1.2.2 研究限制 5
1.3 研究目的 6
1.5 研究大綱 7
第二章 印刷電路板組裝製程與SMT製造技術 9
2.1. PCBA組裝流程簡介 9
2.2. SMT組裝流程 11
2.2.1 錫膏製程製程 13
2.2.2 錫膏印刷輸出檢驗與諸元量測 14
2.2.2 影響錫膏印刷品質之變數 16
2.2.3 錫膏物理與化學特性 18
2.2.4 印刷機參數設計 20
2.2.5 鋼版設計適當性 20
2.3 零件黏貼製程 22
2.4 迴焊製程 22
2.5 TQFP細腳距IC元件 24
2.6 SMT製程改善 25
第三章 實驗設計與預測模型 27
3.1 田口方法 27
3.2 變異數分析 28
3.3 多元迴歸 30
3.4 類神經網路 31
3.5 迴歸樹 34
第四章 錫膏體積預測模型建構與評估 38
4.1 實驗設計 39
4.2 錫膏印刷體積量之預測模型建構 42
4.2.1 多元迴歸模型 43
4.2.2 類神經網路模型 44
4.2.3 迴歸樹模型 46
4.2.4 錫膏體積預測模型之實務績效分析 46
第五章 研究結論與未來研究 50
5.1 研究結論 50
5.2 未來研究方向 51
參考文獻 53
附錄 57

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