臺灣博碩士論文加值系統

本論文分為兩部份，第一部份為一個新型磁滯電流降壓轉換器，主要架構包含有功率電晶體、電流感測電路、取樣與保持電路、磁滯電流比較電路、非重疊電路、驅動電路、補償電路與零電流偵測電路，應用電流感測電路可以全時感測電感電流，並利用零電流偵測電路來提高輕載時的效率。此晶片已由台積電點三五微米兩層多晶矽四層金屬互補式金屬氧化物半導體製程來實現，面積為0.888 mm x 0.949 mm。

本論文第二部份為低壓降電壓調整器，其架構可分為：誤差放大器、傳輸元件、分壓電阻和負載電容。誤差放大器會檢測參考電壓與負迴授信號，誤差放大器經過驅動電路驅動傳輸元件，會依照這二個電壓不同的比例(參考電壓與負迴授信號) 產生輸出電壓。利用誤差放大器與驅動電路建立起負迴授，維持了輸出電壓的位準。在系統單晶片(SOC)中需要快速的暫態響應與低功率消耗，因電流回授會加快暫態響應速度之特性，使用第二代電流傳輸器建立低壓降電壓調整器來提供電流回授與快速暫態響應。

The major research of this thesis can be divided into two parts. In the first part shows the new hysteresis-current-controlled buck converter. It contains some sub-circuiths, inclusive of a power MOS, a current sensing circuit, a sample and hold circuit, a hysteresis-current comparator circuit, a non-overlapping circuit, a driving circuit, a compensator circuit and a zero current detector circuit. The current sensing circuit can fully sense the inductor current and the zero current detector circuit improves effectively at the light load. The proposed circuits have been implemented with TSMC 0.35μm DPQM CMOS processes and the chip area is 0.888mm x 0.949mm with PAD.

In the second part of this thesis, the LDO building block includes an error amplifier, a pass element, an off-chip capacitor and resistors. The error amplifier is used to detect the reference and the feedback voltages. It is generated an output voltage proportional to the difference between these two voltages (reference and feedback voltages), which in turn biases the pass transistor through a base driver circuit. The error amplifier and driver circuit base negative feedback loop that maintains the regulator output voltage at the desired level. Voltage regulators can be used in SOC usually need fast transient response and low power consumption. The current feedback for fast response is provided by Current conveyor II (CCII) based on LDO.

摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xii
第一章 緒論 1
1.1 相關研究發展近況 1
1.2 研究動機與目的 4
1.3 論文架構 6
第二章 直流-直流轉換器的操作原理 7
2.1 切換式降壓轉換器操作原理 7
2.1.1 連續導通模式之穩態分析 8
2.1.2 不連續導通模式之穩態分析 13
2.1.2 邊界模式之穩態分析 16
2.2 低壓降電壓調整器操作原理 18
2.2.1 輸出元件 19
2.2.2 輸入輸出電壓差(Dropout Voltage) 21
2.3 直流-直流轉換器之規格與定義 22
2.3.1 靜態電流(Quiescent Current) 22
2.3.2 效率(Efficiency) 22
2.3.3 輸出電壓漣波(Output Voltage Ripple) 23
2.3.4 線性調節率(Line Regulation) 24
2.3.5 負載調節率(Load Regulation) 24
2.3.6 暫態響應(Transient Response) 24
2.5.7 電源拒斥比(Power Supply Rejection Ration) 26
第三章 新型磁滯電流降壓轉換器的分析與設計 27
3.1 主動式電流感測電路 28
3.2 取樣與保持電路 30
3.3 磁滯電流比較電路 33
3.4 非重疊電路 35
3.5 零電流偵測電路 37
3.6 驅動電路 38
3.7 回授補償電路 40
3.8 整體電路之模擬結果 41
3.8.1 佈局前模擬(Pre-simulation) 42
3.8.2 佈局後模擬(Post-simulation) 47
3.9 整體電路之佈局與實測結果 52
3.9.1 整體電路佈局圖 53
3.9.2 量測環境 55
3.9.3 量測結果 56
第四章 電流回授電壓調整器之電路架構 61
4.1 第二代電流傳輸器基本原理 61
4.2 電流回授之電壓模式低壓降穩壓器設計 64
4.2.1 電路設計架構 64
4.2.2 穩定度與小訊號討論 66
4.2.3 整體電路之模擬結果 68
4.2.3.1 佈局前模擬(Pre-simulation) 68
4.2.3.2 佈局後模擬(Post-simulation) 72
4.2.4 整體電路之佈局與實測結果 75
4.2.4.1 整體電路佈局圖 76
4.2.4.2 量測環境 78
4.2.4.3 量測結果 79
4.3 快速暫態響應之雙迴路控制線性穩壓器設計 84
4.3.1 電路設計架構 84
4.3.2 回授穩定度與頻率補償 86
4.3.3 整體電路之模擬結果 89
4.3.3.1 佈局前模擬(Pre-simulation) 89
4.3.3.2 佈局後模擬(Post-simulation) 92
4.3.4 整體電路之佈局與實測結果 96
4.3.4.1 整體電路佈局圖 97
4.3.4.2 量測環境 99
4.3.4.3 量測結果 100
第五章 結論與未來展望 105
5.1 結論 105
5.2 未來展望 105
參考文獻 106

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