臺灣博碩士論文加值系統

在所有的架構中，快閃式類比數位轉換器 (Flash A/D Converter) 是目前最快的一種架構，然而在提高解析度時，整體面積與消耗功率卻呈現大幅度的增加。因此，管線式類比數位轉換器 (Pipelined A/D Converter) 相較於快閃式類比數位轉換器更適合發展快速與高解析度的架構。管線式類比數位轉換器的效能往往取決於所使用的運算放大器，所以運算放大器的設計常常為管線式類比數位轉換器的設計重點。有別於一般採用運算放大器為核心電路的設計方式，管線式類比數位轉換器的兩個主要電路：前端取樣保持電路(Sample/Hold Circuit)以及相乘式數位類比轉換器(Multiplying DAC)，採用以第二代電流傳輸器(Second-Generation Current Conveyor，CCII)為架構的電路已經被設計出來了。而在訊號傳輸的架構中，採用全差動(Fully Differential)的架構有高雜訊免疫(Noise Rejection)以及兩倍的訊號擺幅(Signal Swing)等優點，因此被廣泛採用於類比數位轉換器中。因此，在此論文中，採用了全差動式電流傳輸器(Fully-Balanced CCII，FBCCII )來設計管線式類比數位轉換器，其中在MDAC的部份，提出了新的電路，來抵抗電荷注入(Charge Injection)的效應。整體電路採用台灣積體電路公司（TSMC）0.18um 1P6M製程來實現，解析度為7位元，取樣頻率為12.5MHz，INLMAX為1.3LSB，DNLMAX為0.7LSB，晶片面積為1.5×1.4mm2。

Among all the ADC architectures, the flash ADC is the fastest one. However, chip area and power consumption grow exponentially as the resolution increases. The pipelined architecture is more suitable for high speed and high resolution applications than the flash architecture. The accuracy of the pipelined ADC greatly depends on OP Amp’s performance. As the result, OP Amp is the most critical circuit when engineers design a pipelined ADC. Unlike the conventional design of pipelined ADC, the sample-and-hold(S/H) circuit and multiplying DAC(MDAC) based on the second-generation current conveyor have been developed instead of the OP Amp. Fully differential architecture is commonly adopted to develop signal process system because of its merits, such as highly noise rejection and double signal swing. Thus, a fully-balanced second -generation current conveyor is adopted to design the pipelined ADC. Besides, a new MDAC is designed to eliminate the effect of charge injection. The pipelined ADC is designed and implemented with TSMC 0.18um 1P6M process. The resolution of the ADC is 7 bits, sampling rate is 12.5Mhz, INLMAX is 1.3LSB, and DNLMAX is 0.7LSB, and chip area is 1.5×1.4mm2.

目 錄

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii

第一章 序論 1
1.1 相關研究發展近況 1
1.2 研究動機 2
1.3 論文架構 2

第二章 管線式類比數位轉換器原理 4
2.1簡介 4
2.2類比數位轉換器效能參數 4
2.2.1 解析度 4
2.2.2 訊號雜訊比 4
2.2.3 訊號對雜訊及失真比 6
2.2.4 動態範圍 6
2.2.5 非線性度 7
2.3類比數位轉換器架構介紹 9
2.3.1 快閃式類比數位轉換器 9
2.3.2 兩段快閃式類比數位轉換器 10
2.3.3 管線式類比數位轉換器 12
2.4管線式類比數位轉換器內部架構介紹 13
2.5數位錯誤校正技術 17
2.5.1 單級1.5位元架構 19

第三章 以電流傳輸器為基礎之管線式類比數位轉換器 22
3.1簡介 22
3.2交換電容技術 22
3.2.1 靴帶式開關 25
3.3第二代電流傳輸器 26
3.4以電流傳輸器為基礎之取樣保持電路 27
3.5以電流傳輸器為基礎之相乘式數位類比轉換器 29
3.5.1 以電流傳輸器為基礎之新型相乘式數位類比轉換器 30
3.6性能比較 32
3.6.1 前端取樣保持電路 32
3.6.2 相乘式數位類比轉換器 34

第四章 以全差動電流傳輸器為基礎之管線式類比數位轉換器 38
4.1簡介 38
4.2全差動第二代電流傳輸器 38
4.2.1 模擬結果 45
4.3比較器 48
4.3.1 單級1.5位元子類比數位轉換器 50
4.3.2 單級2位元子類比數位轉換器 53
4.4前端取樣保持電路 55
4.5相乘式數位類比轉換器 58
4.6單級1.5位元架構 59
4.7時脈產生電路 60
4.8延遲電路與數位錯誤更正電路 61
4.9以全差動電流傳輸器為基礎之管線式類比數位轉換器 63
4.9.1 模擬結果 64

第五章 佈局與測試考量 66
5.1佈局考量 66
5.2測試方法 67
5.2.1 雜訊隔離電路 68
5.2.2 電壓穩壓器 69
5.2.3 差動訊號產生電路 69

第六章 結論 66
6.1結論 66
6.2測試考量 67

參考文獻 72

附錄A
The 2006 VLSI Design/CAD Symposium 投稿論文
『A NEW FBCCII-BASED PIPELINED ANALOG TO DIGITAL
CONVERTER』 76

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