臺灣博碩士論文加值系統

由於JPEG2000是最先進的影像壓縮格式，我們實驗室也致力於開發高效能JPEG2000晶片，並提出比傳統小波離散轉換 (Discrete Wavelet Transform) 更有效率的 QDWT (Quad Discrete Wavelet Transform)。 QDWT的優勢在於可以比傳統DWT提早四分之三的時間將編碼資料送出至下級EBCOT (Embedded Block Coding with Optimized Truncation) 。我們也開發高效能的算數編碼器，採用三級管線的平行化架構達到1 CX-D pair/clock cycle 的輸入率。在本論文中會說明如何透過系統工作流程安排，分析系統內部每塊模組的工作時間，決定出效能最好的系統架構。
為了使我們開發的JPEG2000編碼器更具IP化，我們將其外掛一層AHB (Advanced High-performance Bus) Slave介面。AMBA (Advanced Microcontroller Bus Architecture)為ARM所制定的系統內部匯流排的溝通介面，是目前市面上最常被拿來使用的介面，因此，我們所設計的具有AHB介面的JPEG2000編碼器可應用於任何ARM-based的嵌入式系統。本論文的貢獻在於成功整合一顆具有平行化架構的JPEG2000 Coprocessor，並呈現此架構確實可以大幅提升JPEG2000的效能。此外，也成功的為JPEG2000 Coprocessor掛上AHB 介面，並使之與ARM CPU一起工作，完成整個JPEG2000的編碼流程。

Because JPEG2000 is the state-of-the-art image compression technology, our lab has made efforts in developing a high-performance JPEG2000 chip and developed QDWT (Quad Discrete Wavelet Transform) which is more efficient than the traditional DWT (Discrete Wavelet Transform) . QDWT only needs the quarter of compute time than the traditional DWT does to generate the coefficients to EBCOT (Embedded Block Coding with Optimized Truncation). We also develop a high-performance AC (Arithmetic Entropy Coder). The pipeline architecture is used in the AC and we only use three pipes to reach the input rate, 1 CX-D pair/clock cycle. We will explain that how to organize the best system architecture to achieve small area and high throughputs by arranging the system work flow properly and analyzing the timing of the individual modules.
If the ASIC developed can be popular to be integrated into different systems, the IP issue should be addressed. We wrapped the JPEG2000 Encoder developed by our team in AHB (Advanced High-performance Bus) Slave interface. AMBA, which is drawn up by ARM, is an on-chip communication standard for designing high-performance embedded microcontrollers and is wildly used in the consumer electronic market now. So, the AHB-based JPEG2000 Encoder we developed could be applied in an ARM-based embedded system.
The Contribution of this thesis is to integrate the QDWT, Pass Parallel EBCOT Tier1 and Pipeline AC as a JPEG2000 coprocessor and show this architecture really could improve the performance. Besides, wrap the JPEG2000 coprocessor in AHB slave interface and make it cooperate with ARM CPU to finish the coding procedures of JPEG2000.

Table of Contents
摘要 i
ABSTRACT ii
致謝 iv
Table of Contents v
Lists of Figures ix
Lists of Table xi
Awards xiii
Preface xiv
Chapter 1 System Overview 1
1-1 Introduction 1
1-2 ARM Integrator Platform 1
1-3 System Block Diagram 2
1-3.1 Motherboard (Integrator/AP) 2
1-3.2 Core Module (Integrator/CM920T) 3
1-3.3 Logic Module (Integator/LM-EP20K600E+) 3
Chapter 2 JPEG2000 Coprocessor Hardware Design 4
2-1 Introduction 4
2-2 Main Module Introduction 4
2-2.1 QDWT (Quad Discrete Wavelet Transform) 4
2-2.2 Pass Parallel EBCOT Tier-1 and Arithmetic entropy Coding 5
2-3 JPEG2000 Coprocessor Architecture 6
2-3.1 Analysis the overall system timing 6
2-3.2 Define the module interface I/O and timing properly 8
2-4 Operation Flow Chart 11
2-5 Coprocessor Controller 12
2-5.1 the Control of QDWT 13
2-5.2 The Control of EBCOT 14
2-6 Test Circuit Design 15
2-7 Achievement 18
Chapter 3 Arithmetic Entropy Coding 19
3-1 Introduction 19
3-2 AC Operations 19
3-2.1 Recursive interval subdivision 19
3-2.2 Coding conventions and approximation 20
3-3 Description of the Arithmetic Encoder 21
3-3.1 Encoder code register convention 21
3-3.2 Encoding a decision (ENCODE) 22
3-3.3 Encoding a 1 or a 0 23
3-3.4 Encoding an MPS or LPS (CODEMPS and CODELPS) 24
3-3.5 Probability estimation 27
3-3.6 Renormalization in the encoder (RENORME) 29
3-3.7 Compressed image data output (BYTEOUT) 29
3-3.8 Initialization of the encoder (INITENC) 30
3-3.9 Termination of coding (FLUSH) 31
3-4 Method for Enhance Performance 33
3-5 State Machine 40
3-6 Pin Definition 41
3-7 Timing Diagram 42
3-8 Achievements & Comparison 42
3-8.1 Achievements 42
3-8.2 Comparison 43
Chapter 4 AHB Wrapper Design 44
4-1 Introduction 44
4-2 Work Theory 44
4-2.1 Objectives of the AMBA specification 45
4-2.2 A typical AMBA-based microcontroller 45
4-2.3 AMBA AHB 46
4-2.4 Bus interconnection 47
4-2.5 Overview of AMBA AHB operation 48
4-3 Timing Analysis 49
4-4 AHB JPEG2000 Coprocessor Block Diagram 50
4-5 Register Definition 52
4-6 Work Flow 53
4-7 System Controller Design 54
4-8 Pin Definition 57
4-9 Memory Distribution 59
Chapter 5 Achievements and Perspectives 60
5-1 Achievements 60
5-2 JPEG2000 Codec in the Market 62
5-3 Improvement in the future 65
Reference 68
Appendix 70
A-1 Development Flow 70
A-2 Verification Environment 72
A-3 Pin Map Table for JPEG2000 Coprocessor In Test Mode 73
Lists of Figures
Figure 1 1 Picture of the ARM Integrator Platform 1
Figure 1 2 Overall System Block Diagram 2
Figure 2 1 QDWT encode and output sequence 5
Figure 2 2 the Architecture of JPEG2000 Coprocessor 7
Figure 2 3 JPEG2000 coprocessor operation flowchart 12
Figure 2 4 the control flow for QDWT 14
Figure 2 5 the control flow for EBCOT 15
Figure 2 6 Test mode block diagram 16
Figure 3 1 Encoder for the MQ-coder 22
Figure 3 2 ENCODE procedure 23
Figure 3 3 CODE1 procedure 23
Figure 3 4 CODE0 procedure 24
Figure 3 5 CODELPS procedure with conditional MPS/LPS exchange 25
Figure 3 6 CODEMPS procedure with conditional MPS/LPS exchange 28
Figure 3 7 Encoder renormalization procedure 29
Figure 3 8 BYTEOUT procedure for encoder 30
Figure 3 9 Initialization of the encoder 31
Figure 3 10 FLUSH procedure 32
Figure 3 11 Setting the final bits in the C register 33
Figure 3 12 AC pipeline architecture 34
Figure 3 13 AC encoder state machine 40
Figure 3 14 AC Timing Diagram 42
Figure 4 1 A typical AMBA AHB -based system 46
Figure 4 2 Multiplexer interconnection 47
Figure 4 3 JPEG2000 Coprocessor timing analysis 50
Figure 4 4 AHB-based JPEG2000 Coprocessor block diagram 50
Figure 4 5 Overall system work flow 53
Figure 4 6 System controller flow chart 55
Figure 4 7 System controller state machine 56
Figure 4 8 Memory distribution for JPEG2000 Coprocessor 59


Lists of Table
Table 2 1 JPEG2000 coprocessor pin definition 9
Table 2 2 Pin map table in normal mode 10
Table 2 3 Test Module ID 17
Table 2 4 JPEG2000 coprocessor chip specification 18
Table 3 1 Encoder register structures 21
Table 3 2 Qe values and probability estimation 25
Table 3 3 Pin Definition 41
Table 3 4 comparison with others 43
Table 4 1 Register Definition 52
Table 4 2 AHB-based JPEG2000 chip pin definition 57
Table 5 1 the performance of the JPEG2000 coprocessor on FPGA 60
Table 5 2 the comparison between software and hardware 61
Table 5 3 JPEG2000 coprocessor chip specification 61
Table 5 4 Preliminary IC specification 62
Table 5 5 CS6590 ASIC Cores 64

Table A- 1 DWT Pin Map Table 73
Table A- 2 EBCOT Pin Map Table 74
Table A- 3 FSM Controller Pin Map Table 78
Table A- 4 AC Pin Map Table 79
Table A- 5 CBM Pin Map Table 80
Table A- 6 FIFO&SIPO Pin Map Table 81
Table A- 7 JP2K Top Pin Map Table 82

Reference

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[13] Pei-Chun Chen, “Design of an efficient Pass-Parallel Context Formation Codec for JPEG2000”, National Chiao Tung University, July 2004
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