臺灣博碩士論文加值系統

隨著半導體產業的需求以及發展 ，元件尺寸 必須 不斷地向下微縮， 不斷地向下微縮， 我們在本篇論文 我們在本篇論文 中探討以不同方式來 微縮 多晶矽 無接面電晶體 通道 的優劣，分別為傳統物理 的優劣，分別為傳統物理 的優劣，分別為傳統物理 的優劣，分別為傳統物理 微縮、新 微縮、新 微縮、新 穎的電性微縮 、以及結合了全覆式 閘極構奈米尺度通道的終微縮方。
傳統的物理微縮方式是直接上通道厚度，如此 傳統的物理微縮方式是直接上通道厚度，如此 傳統的物理微縮方式是直接上通道厚度，如此 可以有效的提升 可以有效的提升 無接面電 晶體 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 的開關特性，但是隨著通道尺寸縮小其串聯電阻將會之上升而 導致電流下降。 導致電流下降。 電性微縮的 方式則是在通道下加入一層反向摻雜矽基底，利用 矽基底，利用 矽基底，利用 P/N接面產生體積空 乏的效果，藉此 乏的效果，藉此 乏的效果，藉此 微縮通道厚 度，但伴隨而來的是在後續熱製程中所造成雜質擴散因 度，但伴隨而來的是在後續熱製程中所造成雜質擴散因 度，但伴隨而來的是在後續熱製程中所造成雜質擴散因 度，但伴隨而來的是在後續熱製程中所造成雜質擴散因 度，但伴隨而來的是在後續熱製程中所造成雜質擴散因 此同時 探討元件中 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 主動層和反向摻雜的基底之間 插入了一層 奈米尺度的擴散停止入了一層 奈米尺度的擴散停止抑 制雜質擴散 。研究 。研究 結果發現 結果發現 相較於物理微縮， 相較於物理微縮， 使用 電性微縮的方式 確實 可以獲得提升開 關速度和電流大小，不過 關速度和電流大小，不過 關速度和電流大小，不過 關速度和電流大小，不過 元件的特性對於通道與 基底的濃度和尺寸非常敏感，必須小心 基底的濃度和尺寸非常敏感，必須小心 基底的濃度和尺寸非常敏感，必須小心 設計才能達到有效地提升。然而 設計才能達到有效地提升。然而 設計才能達到有效地提升。然而 ，過高的摻雜濃度會造成嚴重漏電流 過高的摻雜濃度會造成嚴重漏電流 ，以及 隨著元件 通道長度改變其臨界電壓會大幅，這都造成了在 通道長度改變其臨界電壓會大幅，這都造成了在 通道長度改變其臨界電壓會大幅，這都造成了在 通道長度改變其臨界電壓會大幅，這都造成了在 實際電路 應用上的困難，因此提出 應用上的困難，因此提出 應用上的困難，因此提出 使用基極偏壓 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 的方式來應用此類型電晶體， 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 透過基極偏壓可以有效調整元件電性 (ϒ=0.306 )，因此在認為 ，因此在認為 ，因此在認為 電性微縮結合 基極偏壓是 更合適 的應用。 的應用。 終極微縮方式 中，元 件結合全覆式閘極與奈米尺度的通道， 件結合全覆式閘極與奈米尺度的通道， 展現最佳 的開關特性 (S.S. ≈66mV/dec )及電流大小 (ION ≈79 µA/µm A/µm)。因此，全覆式閘極結構依舊是 因此，全覆式閘極結構依舊是 最

For the demands and developments of semiconductor industry, the device dimension is scaled down continuously. In this dissertation, we investigate the pros and cons of the multi-gate poly-Si junctionless transistors in the various scaling routes. The routes are conventionally physical scaling, novel electrical scaling, and ultimate scaling, respectively.
In the conventional physical scaling route, thinning down the channel of junctionless transistor is able to enhance the switching ability, but its series resistance arise to cause the current declines as the channel dimension scaling down. In the electrical scaling route, the inverse doped poly-Si body is inserted under the channel. The P/N junction supports the volume depletion to scale the channel down, but there is dopant diffusion after the subsequent thermal process. Therefore, we also investigate the impacts of the insertion of a nano-scale dielectric for suppressing diffusion. Consequently, the switching characteristic and current level actually are improved by electrical scaling, but the channel and body concentration is a critical factor to the electrical characteristic. However, too heavy doping concentration leading serious leakage and VT roll-off as channel length increases are still unsolved issues, which make the devices hard to apply on the real circuits. Body bias can adjust the electrical characteristic efficiently (ϒ=0.306) and extend the device application. In the ultimate scaling route, the device combined with the GAA architecture and nano-scale channels shows the superior S.S (≈66mV/dec). and current level (ION ≈79 µA/µm). As a result, the GAA architecture is still the best choice in the various scaling routes.

摘要 i
Abstract ii
致謝 iii
Contents iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
1.1 General Background 1
1.1.1 Polycrystalline Silicon Thin-film Transistors 1
1.1.2 Junctionless Transistors 2
1.1.3 Multi-gate Architecture 3
1.1.4 Inverse Doped Layer below the Channels 4
1.2 Motivation 5
1.3 Organization of the Research 6
Chapter 2 Investigation of the Various Scaling Routes on n-type Multi-gate Poly-Si Junctionless Transistors 12
2.1 Literature Review 12
2.2 Experimental Procedure 12
2.3 Results and Discussion 14
2.3.1 SEM and TEM images 14
2.3.2 Physical Scaling Route 14
2.3.3 Electrical Scaling Route 15
2.3.3.1 VD-JLTs with Dopant Diffusion 15
2.3.3.2 The Impacts of the Diffusion Stop Layer 17
2.3.4 Comparison with the Various Scaling Routes 18
2.4 Summary 19
Chapter 3 Investigation of the Electrical Scaling Route on n-/p-type Multi-gate Poly-Si Junctionless Transistors 36
3.1 Introduction and Motivation 36
3.2 Experimental Procedure 36
3.3 Results and Discussion 38
3.3.1 SEM and TEM images 38
3.3.2 NMOS in the Various Scaling Routes 39
3.3.3 Comparison of Different Type VD-FinFET 40
3.3.4 The Drawbacks of the Electrical Scaling Route and the Extensive Application 43
3.4 Summary 44
Chapter 4 Conclusion and Future Works 58
4.1 Conclusion 58
4.2 Future Works 59
References 61
Publication List 65

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