臺灣博碩士論文加值系統

自動測試機台(ATE)被使用來測試積體電路(Integrated Circuit, IC)的性能與功能，避免缺陷的IC流入市場。格式器(Formatter)在自動測試機台裡是相當重要的核心模組，其負責讀取使用者定義的符號資料(Symbol Data)，以產生待測電路所需的測試波形。
本論文提出新的符號生成方法與時間設置表/格式設置表，將多通道格式器實作於Xilinx Spatan-6 FPGA中，利用特別設計的可程式化延遲線作為時序電路，可精準的控制邊緣放置的時間點，並透過校準機制可提升邊緣放置的準確度。
最後，本論文實作的16個通道FPGA格式器，其具有100 Msps符號產生頻率、200 ps邊緣擺置解析度與積分非線性誤差小於0.5 LSB的高精確度。

Automatic Test Equipment (ATE) is used to test the performance and features of the Inte-grated Circuit, and avoiding the defective ICs from entering to the market.
Formatter in the ATE is the vital core module to load the symbol data by user’s defi-nition, and then generate the testing waveform for the circuit which should be measured.
In this paper, it proposes a new way to generate the new symbol and time/format set table, and implements the muti-channel formatter on Xilinx Spatan-6 FPGA board. Using the especially designed for the programmable delay line as a sequential circuit, it can ac-curate control the timing of edge placement, and improve the accuracy of edge placement by calibration mechanism.
At last, the 16-channel FPGA formatter implemented in this paper has 100 Msps generation frequency, 200 ps edge placement resolution, and high accuracy with the inte-gral nonlinearity error less than 0.5 LSB.

口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
目錄 v
圖目錄 viii
表目錄 xi
第1章 緒論 1
1.1 研究動機與目的 1
1.2 相關研究 2
1.3 研究貢獻 3
1.4 論文架構 3
第2章 格式器介紹與先前研究 4
2.1 自動測試機台(Automatic Test Equipment, ATE) 4
2.2 格式器(Formatter) 5
2.3 先前研究 7
2.3.1 格式器原型架構(Formatter Prototype Architecture) 7
2.3.2 符號伸展功能 9
2.3.3 邊緣產生器池概念(Edge Generator Pool Concept) 10
2.3.4 多通道格式器架構 12
2.3.5 可程式化延遲線(Programmable Delay Line)與校準(Calibration) 14
2.3.6 現場可程式化邏輯陣列(Field-Programmable Gate Array) 17
第3章 自動測試機台之符號定義 19
3.1 符號資料(Symbol Data)定義與編碼方式 19
3.2 邊緣產生器(EG)與邊緣產生器池(EG-pool) 21
3.3 時間設置表(Time Set Table)和格式設置表(Format Set Table) 24
3.3.1 時間設置表(Time Set Table) 24
3.3.2 邊緣時序(Edge Timing) 25
3.3.3 格式設置表(Format Set Table) 26
3.4 符號產生流程 27
3.5 符號資料與設置表的優點 28
3.5.1 降低FPGA內部資源使用率 28
3.5.2 邊緣解析度不會受到伸展的影響 30
3.5.3 方便整合格式器與接收器 31
第4章 16通道格式器之架構 33
4.1 多通道格式器架構 34
4.1.1 邊緣產生器池控制器(EG-pool Controller) 34
4.1.2 邊緣組合器(Edge Combiner) 40
4.1.3 轉態時序範例 41
4.1.4 定序器(Sequencer) 42
4.2 軟體預處理(Software Pre-processing) 45
4.2.1 測量通道內共8個邊緣產生器之所有延遲值 45
4.2.2 每個邊緣產生器根據所需間距挑選出線性度較好的延遲值 47
4.2.3 將邊緣產生器進行分成兩組，並建立兩組邊緣產生器優先序表 48
4.2.4 使用API將使用者資料進行格式轉換 48
4.3 電腦端之LabVIEW操作機制 49
第5章 實驗結果 51
5.1 實驗環境 51
5.2 延遲線之設計與實驗結果 52
5.3 多通道格式器之效能分析 55
5.4 格式器之功能驗證 57
5.4.1 邊緣佈局(Edge Placement) 57
5.4.2 多通道之對齊(Alignment)機制 61
5.4.3 輸出波形示範(Waveform Demonstration) 63
5.5 FPGA格式器佈局(Layout) 66
5.6 資源使用量與功率消耗(Resource Utilization & Power Consumption) 67
第6章 結論與未來研究方向 69
6.1 結論 69
6.2 未來研究方向 69
參考文獻 70

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